US-12620444-B2 - Operation method for three-dimensional flash memory including ferroelectric-based data storage pattern and back gate

US12620444B2US 12620444 B2US12620444 B2US 12620444B2US-12620444-B2

Abstract

Disclosed is an operation method for a three-dimensional flash memory including a ferroelectric-based data storage pattern and a back gate. According to an embodiment, the operation method for a program of a three-dimensional flash memory may comprise the steps of: applying a program voltage to a selected word line corresponding to a target memory cell for program operation from among word lines; floating each of unselected word lines other than the selected word line from among the word lines; applying a pass voltage to a back gate of a selected vertical channel structure including the target memory cell from among vertical channel structures; and performing program operation on the target memory cell, in response to the application of the program voltage to the selected word line, the floating of each of the unselected word lines, and the application of the pass voltage to the back gate.

Inventors

Yun Heub Song
Jea Min SHIM

Assignees

IUCF-HYU (INDUSTRY-UNIVERSITY COOPERATION FOUNDATION HANYANG UNIVERSITY)

Dates

Publication Date: 20260505
Application Date: 20240808
Priority Date: 20220211

Claims (7)

1 . A method of operating a program of a three-dimensional flash memory including word lines formed to extend in a horizontal direction on a substrate, spaced apart from each other in a vertical direction, and laminated and vertical channel structures passing through the word lines and extending in the vertical direction, wherein each of the vertical channel structures includes a vertical channel pattern formed to extend in the vertical direction, a back gate formed to cover an inner wall of the vertical channel pattern and extend in the vertical direction, and a ferroelectric-based data storage pattern formed to cover an outer wall of the vertical channel pattern, and the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, the method comprising: applying a program voltage to a selected word line corresponding to a target memory cell that is a target of a program operation among the word lines; floating each of unselected word lines except for the selected word line among the word lines; applying a pass voltage to a back gate of a selected vertical channel structure including the target memory cell among the vertical channel structures; and performing the program operation on the target memory cell in response to the program voltage being applied to the selected word line, the unselected word lines being floating, and the pass voltage being applied to the back gate.
2 . The method of claim 1 , further comprising: applying a voltage for self-boosting a vertical channel pattern of an unselected vertical channel structure to a bit line of the unselected vertical channel structure not including the target memory cell among the vertical channel structures.
3 . The method of claim 1 , wherein, when the vertical channel pattern of the selected vertical channel structure including the target memory cell is of an N type, the applying of the program voltage to the selected word line includes applying a positive program voltage, and the applying of the pass voltage to the back gate of the selected vertical channel structure includes applying a positive pass voltage.
4 . The method of claim 1 , wherein, when the vertical channel pattern of the selected vertical channel structure including the target memory cell is of a P type, the applying of the program voltage to the selected word line includes applying a negative program voltage, and the applying of the pass voltage to the back gate of the selected vertical channel structure includes applying a negative pass voltage.
5 . A method of erasing a three-dimensional flash memory including word lines formed to extend in a horizontal direction on a substrate, spaced apart from each other in a vertical direction, and laminated and vertical channel structures passing through the word lines and extending in the vertical direction, wherein each of the vertical channel structures includes a vertical channel pattern formed to extend in the vertical direction, a back gate formed to cover an inner wall of the vertical channel pattern and extend in the vertical direction, and a ferroelectric-based data storage pattern formed to cover an outer wall of the vertical channel pattern, and the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, the method comprising: applying an erasure voltage for generating gate induced drain leakage (GIDL) with respect to a string selection line (SSL) to a bit line of each of vertical channel structures included in a block that is a target of an erasure operation among the vertical channel structures; applying a ground voltage to each of the word lines; floating a back gate of each of the vertical channel structures included in the block; and performing the erasure operation on memory cells of each of the vertical channel structures included in the block in response to the GIDL being generated in each of the vertical channel structures included in the block.
6 . The method of claim 5 , wherein, when the vertical channel pattern of each of the vertical channel structures included in the block is of an N type, the applying of the erasure voltage includes applying a positive erasure voltage.
7 . The method of claim 5 , wherein, when the vertical channel pattern of each of the vertical channel structures included in the block is of a P type, the applying of the erasure voltage includes applying a negative erasure voltage.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of pending PCT International Application No. PCT/KR2023/000995, which was filed on Jan. 20, 2023, and which claims priority to Korean Patent Application No. 10-2022-0017916 which was filed in the Korean Intellectual Property Office on Feb. 11, 2022. The disclosures of which are hereby incorporated by reference in their entireties. TECHNICAL FIELD The following embodiments relate to a method of operating a three-dimensional flash memory, and more particularly, to a technology for a method of operating a three-dimensional flash memory including a ferroelectric-based data storage pattern and a back gate. BACKGROUND ART A flash memory element that is an electrically erasable programmable read only memory (EEPROM) electrically controlling data input/output through an F-N (Fowler-Nordheim) tunneling or a hot electron injection may be used in common in a computer, a digital camera, an MP3 player, a game system, a memory stick, etc. In this flash memory element, it is required to increase an integration degree in order to satisfy excellent performance and low price required by consumers. Thus, a three dimensional structure in which memory cell transistors are vertically arranged to constitute a memory cell string CSTR is proposed. In the three-dimensional flash memory, since the recent trend is to reduce a cross-sectional area of the memory cell string CSTR for integration, a technology in which a single film made of a ferroelectric material is used instead of a blocking oxide-nitride-tunnel oxide ONO used as a data storage pattern DSP has been proposed. However, research and development on a method of operating a three-dimensional flash memory using the data storage pattern DSP based on ferroelectric is insufficient. Meanwhile, a structure in which a back gate BG is disposed on an inner wall of a vertical channel pattern VCP is proposed to solve the problem that, during a program operation, the program operation of a target memory cell (Sel memory cell) is disturbed by a pass voltage VPASS applied to each of unselected word lines (Unsel WLs) adjacent to a selected word line (Sel WL) of the target memory cell (Sel memory cell). However, research and development on the method of operating the three-dimensional flash memory having a back gate (BG) structure is also insufficient. Accordingly, in the following embodiments, the method of operating the three-dimensional flash memory including the ferroelectric-based data storage pattern DSP and the back gate BG is proposed. DETAILED DESCRIPTION OF THE INVENTION Technical Problem Embodiments propose a method of operating a three-dimensional flash memory including the ferroelectric-based data storage pattern DSP and a back gate BG to solve a problem that a program operation of the target memory cell (Sel memory cell) is disturbed by the pass voltage VPASS applied to each of the unselected word lines (Unsel WLs) while improving horizontal scaling. However, technical problems to be solved by the present disclosure are not limited to the above problems and may be variously expanded without departing from the technical spirit and scope of the present disclosure. Technical Solution According to an embodiment, there is provided a method of operating a program of a three-dimensional flash memory including word lines formed to extend in a horizontal direction on a substrate, spaced apart from each other in a vertical direction, and laminated and vertical channel structures passing through the word lines and extending in the vertical direction, wherein each of the vertical channel structures includes a vertical channel pattern formed to extend in the vertical direction, a back gate formed to cover an inner wall of the vertical channel pattern and extend in the vertical direction, and a ferroelectric-based data storage pattern formed to cover an outer wall of the vertical channel pattern, and the data storage pattern and the vertical channel pattern constitute memory cells corresponding to the word lines, the method including applying a program voltage to a selected word line corresponding to a target memory cell that is a target of a program operation among the word lines, floating each of unselected word lines except for the selected word line among the word lines, applying a pass voltage to a back gate of a selected vertical channel structure including the target memory cell among the vertical channel structures, and performing the program operation on the target memory cell in response to the program voltage being applied to the selected word line, the unselected word lines being floating, and the pass voltage being applied to the back gate. According to an aspect, the method may further include applying a voltage for self-boosting a vertical channel pattern of an unselected vertical channel structure to a bit line of the unselected vertical channel structure not including the target memory cell among the