US-12620445-B2 - Controlling erase-to-program delay for improving data retention

Abstract

A memory device includes a memory array and control logic, operatively coupled to the memory array, to perform operations including identifying an erased block of the memory array, causing a set of cells addressable by a target wordline of the erased block to be set to a target threshold voltage, determining an amount of threshold voltage shift with respect to the target threshold voltage after a delay, determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric, and in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.

Inventors

• Zhongyuan Lu

Assignees

• MICRON TECHNOLOGY, INC.

Dates

Publication Date

20260505

Application Date

20231122

Claims (20)

1. 1 . A memory device comprising: a memory array; and control logic, operatively coupled to the memory array, to perform operations comprising: identifying an erased block of the memory array; causing, at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state; determining an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay; determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric; and in response to determining that the amount of threshold voltage shift is sufficient, releasing the erased block for programming.
2. 2 . The memory device of claim 1 , wherein the erased block is erased and the set of cells is programmed in accordance with a non-zero delay erase policy.
3. 3 . The memory device of claim 1 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a lookup table.
4. 4 . The memory device of claim 1 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a function.
5. 5 . The memory device of claim 1 , wherein causing the set of cells to be programmed comprises causing a programming pulse to be applied to the target wordline with a programming voltage to generate a data pattern that defines a target wordline activation energy.
6. 6 . The memory device of claim 1 , wherein determining the amount of threshold voltage shift comprises causing a scan operation to be performed with respect to the target wordline.
7. 7 . The memory device of claim 1 , wherein the operations further comprise: in response to determining that the amount of threshold voltage shift does not satisfy the threshold condition, re-determining the amount of threshold voltage shift after the delay.
8. 8 . A method comprising: identifying, by a processing device, an erased block of a memory device; causing, by the processing device at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state; determining, by the processing device, an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay; determining, by the processing device, whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric; and in response to determining that the amount of threshold voltage shift is sufficient, releasing, by the processing device, the erased block for programming.
9. 9 . The method of claim 8 , wherein the erased block is erased and the set of cells is programmed in accordance with a non-zero delay erase policy.
10. 10 . The method of claim 8 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a lookup table.
11. 11 . The method of claim 8 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a function.
12. 12 . The method of claim 8 , wherein causing the set of cells to be programmed comprises causing a programming pulse to be applied to the target wordline with a programming voltage to generate a data pattern that defines a target wordline activation energy.
13. 13 . The method of claim 8 , wherein determining the amount of threshold voltage shift comprises causing a scan operation to be performed with respect to the target wordline.
14. 14 . The method of claim 8 , further comprising: in response to determining that the amount of threshold voltage shift does not satisfy the threshold condition, re-determining, by the processing device, the amount of threshold voltage shift after the delay.
15. 15 . A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying an erased block of a memory array; causing, at a first time, a set of cells addressable by a target wordline of the erased block to be programmed to a target threshold voltage different from an erase state; determining an amount of threshold voltage shift with respect to the target threshold voltage at a second time after the first time, wherein a difference between the second time and the first time is defined by a delay; determining whether the amount of threshold voltage shift satisfies a threshold condition defined by a target data retention metric; and in response to determining that the amount of threshold voltage shift does not satisfy the threshold condition, re-determining the amount of threshold voltage shift after the delay.
16. 16 . The non-transitory computer-readable storage medium of claim 15 , wherein the erased block is erased and the set of cells is programmed in accordance with a non-zero delay erase policy.
17. 17 . The non-transitory computer-readable storage medium of claim 15 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a lookup table.
18. 18 . The non-transitory computer-readable storage medium of claim 15 , wherein the amount of threshold voltage shift corresponds to a data retention metric determined using a function.
19. 19 . The non-transitory computer-readable storage medium of claim 15 , wherein causing the set of cells to be programmed comprises causing a programming pulse to be applied to the target wordline with a programming voltage to generate a data pattern that defines a target wordline activation energy.
20. 20 . The non-transitory computer-readable storage medium of claim 15 , wherein the operations further comprise: in response to determining that the amount of threshold voltage shift satisfies the threshold condition, releasing the erased block for programming.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) The present application claims the benefit of U.S. Provisional Patent Application No. 63/438,570, filed on Jan. 12, 2023 and entitled “CONTROLLING ERASE-TO-PROGRAM DELAY FOR IMPROVING DATA RETENTION”, the entire contents of which are hereby incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to controlling erase-to-program delay for data retention to enhance performance and reliability. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIG. 1A illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 1B illustrates an example block diagram of a memory device in communication with a memory sub-system controller of a memory sub-system, in accordance with some embodiments of the present disclosure. FIGS. 2A-2C are diagrams of portions of an example array of memory cells included in a memory device, in accordance with some embodiments of the present disclosure. FIG. 3 is a flow diagram of an example method to control erase-to-program delay for data retention, in accordance with some embodiments of the present disclosure. FIGS. 4-5 illustrate example systems for applying a non-zero delay erase policy, in accordance with some embodiments of the present disclosure. FIG. 6 illustrates an example block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to controlling erase-to-program delay for improving data retention. A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1A. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a not-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1A. A non-volatile memory device is a package of one or more dies. Each die can include one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes of a set of physical blocks. Each block includes of a set of pages. Each page includes of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1,” or combinations of such values. A memory device can be arranged in a two-dimensional or a three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of A wordline can have a row of associated memory cells in a memory device that are used with one or more bitlines to generate the address of each of the memory cells. The intersection of a bitline and wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device in order to allow concurrent operations to take place on each plane. A block of data can correspond to one or more data addresses in the memory device (e.g., a block, a plurality of blocks, a plurality of cells, etc.). The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages of two or more memory planes, including differen