US-12620447-B2 - Adaptive temperature compensation for a memory device

US12620447B2US 12620447 B2US12620447 B2US 12620447B2US-12620447-B2

Abstract

A system includes a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations including: receiving a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to determining that the second temperature falls in the temperature range comprising the first temperature, adjusting, based on the offset value, a temperature compensation value used in the second error handling operation.

Inventors

Patrick R. KHAYAT
Hyungseok Kim
Steven Michael Kientz
Zixiang Loh
Jun Wan

Assignees

MICRON TECHNOLOGY, INC.

Dates

Publication Date: 20260505
Application Date: 20240628

Claims (20)

1 . A system comprising: a memory device; and a processing device, operatively coupled to the memory device, the processing device to perform operations comprising: receiving a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to determining that the second temperature falls in the temperature range comprising the first temperature, adjusting, based on the offset value, a temperature compensation value used in the second error handling operation.
2 . The system of claim 1 , wherein a second temperature compensation value used in the second error handling operation is equal to a first temperature compensation value used in the first error handing operation.
3 . The system of claim 2 , wherein the second temperature compensation value used in the second error handling operation is calculated based on the offset value and a default value of the temperature compensation coefficient.
4 . The system of claim 2 , wherein the first temperature compensation value used in the first error handing operation is calculated based on a default value of the temperature compensation coefficient.
5 . The system of claim 1 , wherein adjusting the temperature compensation value used in the subsequent operation further comprises: making a second temperature compensation value used in the second error handling operation equal a first temperature compensation value used in the first error handing operation.
6 . The system of claim 1 , wherein the operations further comprise: storing the temperature range and the offset value in a data structure, wherein the data structure comprises a plurality of entries, each entry corresponding to a respective parameter of the set of parameters and the first temperature.
7 . The system of claim 1 , wherein each of the set of the memory cells comprises a multi-level memory cell and is configured to store a charge corresponding to one of a plurality of voltage levels, each of the plurality of voltage levels representing a corresponding logical data value, and wherein the set of parameters corresponds to at least one of the plurality of voltage levels.
8 . The system of claim 1 , wherein the set of parameters corresponds to at least one of: a sensing time, a source plate potential, and at least one of a plurality of wordline groups.
9 . The system of claim 1 , wherein the operations further comprise: responsive to determining that the second temperature is outside of the temperature range of the first temperature, using a default temperature compensation value in the second error handling operation.
10 . The system of claim 1 , wherein the operations further comprise: restoring the adjusted temperature compensation value to a default value responsive to completing the error handling flow.
11 . A method comprising: receiving, by a processing device, a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to determining that the second temperature falls in the temperature range comprising the first temperature, adjusting, based on the offset value, a temperature compensation value used in the second error handling operation.
12 . The method of claim 11 , wherein a second temperature compensation value used in the second error handling operation is equal to a first temperature compensation value used in the first error handing operation, wherein the second temperature compensation value used in the second error handling operation is calculated based on the offset value and a default value of the temperature compensation coefficient, and wherein the first temperature compensation value used in the first error handing operation is calculated based on the default value of the temperature compensation coefficient.
13 . The method of claim 11 , wherein adjusting the temperature compensation value used in the subsequent operation further comprises: making a second temperature compensation value used in the second error handling operation equal a first temperature compensation value used in the first error handing operation.
14 . The method of claim 11 , further comprising: storing the temperature range and the offset value in a data structure.
15 . The method of claim 14 , wherein the data structure comprises a plurality of entries, each entry corresponding to a respective parameter of the set of parameters and the first temperature.
16 . The method of claim 11 , wherein each of the set of the memory cells comprises a multi-level memory cell and is configured to store a charge corresponding to one of a plurality of voltage levels, each of the plurality of voltage levels representing a corresponding logical data value, and wherein the set of parameters corresponds to at least one of the plurality of voltage levels.
17 . The method of claim 11 , wherein the set of parameters corresponds to at least one of: a sensing time, a source plate potential, and at least one of a plurality of wordline groups.
18 . The method of claim 11 , wherein determining the first temperature further comprises measuring the first temperature during the first error handing operation.
19 . The method of claim 11 , further comprising: restoring the adjusted temperature compensation value to a default value responsive to completing the error handling flow.
20 . A non-transitory computer readable storage medium including instructions that, when executed by a processing device, cause the processing device to perform operations comprising: receiving a request to perform a read operation, the request identifying a set of memory cells in a portion of a memory device; determining a first temperature of the set of memory cells, wherein the first temperature is associated with a first error handing operation of an error handling flow directed to the set of memory cells; determining an offset value to be applied to a temperature compensation coefficient of a parameter of a set of parameters associated with the set of memory cells, wherein the offset value is associated with a temperature range comprising the first temperature; determining a second temperature of the set of memory cells, wherein the second temperature is associated with a second error handling operation following the first error handing operation of the error handling flow directed to the set of memory cells; and responsive to determining that the second temperature falls in the temperature range comprising the first temperature, adjusting, based on the offset value, a temperature compensation value used in the second error handling operation.

Description

RELATED APPLICATIONS This application claims the benefit of U.S. Provisional Patent Application No. 63/524,995, filed Jul. 5, 2023, the entire contents of which are incorporated by reference herein. TECHNICAL FIELD Embodiments of the disclosure relate generally to memory sub-systems, and more specifically, relate to adaptive temperature compensation for a memory device. BACKGROUND A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices. BRIEF DESCRIPTION OF THE DRAWINGS The disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure. The drawings, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only. FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure. FIG. 2 is a flow diagram of an example method of adaptive temperature compensation, in accordance with some embodiments of the present disclosure. FIGS. 3A-3C illustrate examples of data for adaptive temperature compensation, in accordance with some embodiments of the present disclosure; FIG. 4 illustrates an example of a table including a set of parameters for adaptive temperature compensation, in accordance with some embodiments of the present disclosure; FIG. 5 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION Aspects of the present disclosure are directed to adaptive temperature compensation for a memory device. A memory sub-system can be a storage device, a memory module, or a combination of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1. In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system. A memory sub-system can include high density non-volatile memory devices where retention of data is desired when no power is supplied to the memory device. One example of non-volatile memory devices is a negative-and (NAND) memory device. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1. A non-volatile memory device is a package of one or more dies. Each die can consist of one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. Each block consists of a set of pages. Each page consists of a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information, and has various logic states that correlate to the number of bits being stored. The logic states can be represented by binary values, such as “0” and “1”, or combinations of such values. A memory device can include multiple memory cells arranged in a two-dimensional or a three-dimensional grid. Memory cells are formed onto a silicon wafer in an array of columns and rows. A memory device can further include conductive lines connected to respective ones of the memory cells, referred to as wordlines and bitlines. The intersection of a bitline and a wordline constitutes the address of the memory cell. A block hereinafter refers to a unit of the memory device used to store data and can include a group of memory cells, a wordline group, a wordline, or individual memory cells. One or more blocks can be grouped together to form a plane of the memory device in order to allow concurrent operations to take place on each plane. The memory device can include circuitry that performs concurrent memory page accesses of two or more memory planes. For example, the memory device can include multiple access line driver circuits and power circuits that can be shared by the planes of the memory device to facilitate concurrent access of pages of two or more memory planes, including different page types. For ease of description, these circuits can be generally referred to as independent plane driver circuits. Depending on the storage architecture employed, data can be stored across the memory planes (i.e., in stripes). Accordingly, one request to read a segment of data (e.g., corresponding to one or more data addresses) can result in read operations performed on two or more of the memory planes of the memory device. Various data operations can be performed by the memory sub-system. The data operations can be host-initiated oper