US-12620448-B2 - Solid state drive (SSD) with in-flight erasure iteration suspension

US12620448B2US 12620448 B2US12620448 B2US 12620448B2US-12620448-B2

Abstract

An apparatus is described. The apparatus includes a memory chip having logic circuitry to suspend application of an erasure voltage, wherein, respective responses of the erasure voltage to a decision to suspend the application of the erasure voltage depend on where the erasure voltage is along its waveform.

Inventors

Justin R. DAYACAP
Shantanu R. Rajwade
Kyung Jean YOON
Ali Khakifirooz
David J. Pelster
Yogesh B. Wakchaure
Xin Guo

Assignees

SK HYNIX NAND PRODUCT SOLUTIONS CORP.

Dates

Publication Date: 20260505
Application Date: 20240624

Claims (18)

1 . An apparatus, comprising: a memory; and a hardware processor coupled to the memory and configured at least to: apply an erase voltage to one or more storage cells; while applying the erase voltage to the one or more storage cells: receive a command to suspend applying the erase voltage to the one or more storage cells; determine that the erase voltage exceeds a critical voltage; determine that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold; and in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold: continue to apply the erase voltage to the one or more storage cells for a first period of time; and suspend applying the erase voltage to the one or more second storage cells after the first period of time.
2 . The apparatus of claim 1 wherein the command to suspend applying the erase voltage to the one or more storage cells is received from a solid state drive (SSD) controller.
3 . The apparatus of claim 1 , wherein the hardware processor is further configured to: receive additional commands during the first period of time, wherein the additional commands include one or more read commands.
4 . The apparatus of claim 1 wherein the hardware processor is further configured to: receive additional commands after the one or more storage cells are erased.
5 . The apparatus of claim 1 , further comprising register space to store at least: a first value of the critical voltage; and a second value of the first predetermined threshold.
6 . The apparatus of claim 1 , wherein the hardware processor is further configured to: apply a second erase voltage to one or more second storage cells; while applying the second erase voltage to the one or more second storage cells: receive a second command to suspend applying the second erase voltage to the one or more second storage cells; and determine that the second erase voltage does not exceed the critical voltage; and in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells and determining that the second erase voltage does not exceed the critical voltage, suspend applying the second erase voltage to the one or more second storage cells for a second period of time.
7 . The apparatus of claim 1 wherein the erase voltage is constant for at least a portion of the amount of time.
8 . The apparatus of claim 1 , wherein the hardware processor is further configured to: apply a second erase voltage to one or more second storage cells; and while applying the second erase voltage to the one or more second storage cells: receive a second command to suspend applying the second erase voltage to the one or more second storage cells; determine that the second erase voltage does not exceed the critical voltage; in response to determining that the second erase voltage does not exceed the critical voltage, determine that a count of erase suspensions has reached a threshold of erase suspensions; in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells and determining that the count of erase suspensions has reached the threshold of erase suspensions: determine not to suspend applying the second erase voltage to the one or more second storage cells; and continue to apply the second erase voltage to the one or more second storage cells until the one or more second storage cells are erased.
9 . A method, comprising: applying an erase voltage to one or more storage cells; while applying the erase voltage to the one or more storage cells: receiving a command to suspend applying the erase voltage to the one or more storage cells; determining that the erase voltage exceeds a critical voltage; determining that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold; and in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold: continuing to apply the erase voltage to the one or more storage cells for a first period of time; and suspending applying the erase voltage to the one or more storage cells after the first period of time.
10 . The method of claim 9 further comprising: receiving additional commands after the one or more storage cells are erased.
11 . The method of claim 9 further comprising: storing in a register space at least: a first value of the critical voltage; and a second value of the first predetermined threshold.
12 . The method of claim 9 further comprising: applying a second erase voltage to one or more second storage cells; and while applying the second erase voltage to the one or more second storage cells: receiving a second command to suspend applying the second erase voltage to the one or more second storage cells; and determining that the second erase voltage does not exceed the critical voltage; and in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells and determining that the second erase voltage does not exceed the critical voltage, suspending applying the second erase voltage to the one or more second storage cells for a second period of time.
13 . The method of claim 9 wherein the erase voltage is constant for at least a portion of the amount of time.
14 . The method of claim 9 , further comprising: applying a second erase voltage to one or more second storage cells; and while applying the second erase voltage to the one or more second storage cells: receiving a second command to suspend applying the second erase voltage to the one or more second storage cells; determining that the second erase voltage does not exceed the critical voltage; in response to determining that the second erase voltage does not exceed the critical voltage, determining that a count of erase suspensions has reached a threshold of erase suspensions; in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells and determining that the count of erase suspensions has reached the threshold of erase suspensions: determining not to suspend applying the second erase voltage to the one or more second storage cells; and continuing to apply the second erase voltage to the one or more second storage cells until the one or more second storage cells are erased.
15 . A non-transitory computer-readable medium containing computer executable instructions that, when executed by a processor, cause the processor to perform a method, the method comprising: applying an erase voltage to one or more storage cells; and while applying the erase voltage to the one or more storage cells: receiving a command to suspend applying the erase voltage to the one or more storage cells; determining that the erase voltage exceeds a critical voltage; determining that an amount of time during which the erase voltage exceeds the critical voltage does not meet a first predetermined threshold; and in response to receiving the command to suspend applying the erase voltage to the one or more storage cells, determining that the erase voltage exceeds the critical voltage, and determining that the amount of time during which the erase voltage exceeds the critical voltage does not meet the first predetermined threshold: continuing to apply the erase voltage to the one or more storage cells for a first period of time; and suspending applying the erase voltage to the one or more storage cells after the first period of time.
16 . The non-transitory computer-readable medium of claim 15 , wherein the command to suspend applying the erase voltage to the one or more storage cells is received from a solid state drive controller.
17 . The non-transitory computer-readable medium of claim 15 , wherein the method further comprises: applying a second erase voltage to one or more second storage cells; while applying the second erase voltage to the one or more second storage cells: receiving a second command to suspend applying the second erase voltage to the one or more second storage cells; determining that the second erase voltage does not exceed the critical voltage; and in response to receiving the second command to suspend applying the second erase voltage to the one or more second storage cells and determining that the second erase voltage does not exceed the critical voltage, suspending applying the second erase voltage to the one or more second storage cells for a second period of time; and receiving additional commands during the second period of time, wherein the additional commands include one or more read commands.
18 . The non-transitory computer-readable medium of claim 15 , wherein the method further comprises: receiving additional commands after the one or more storage cells are erased.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a continuation of U.S. patent application Ser. No. 16/727,794, filed Dec. 26, 2019, which is hereby incorporated by reference herein in its entirety. FIELD OF INVENTION The field of invention pertains generally to the computing sciences, and, more specifically to a solid state drive (SSD) with in-flight erasure iteration suspension. BACKGROUND With the emergence of cloud-computing, machine learning, artificial intelligence and other “big-data” applications, the performance of non volatile mass storage has become a keen area of focus as the ability of these applications to execute as desired by their customers depends on the ability of mass storage to quickly respond to high rates of commands. As such, SSD designers are constantly seeking ways to improve the performance of their SSD devices. FIGURES A better understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings, in which: FIG. 1 (prior art) depicts a flash memory erasure process; FIG. 2 (prior art) depicts another flash memory erasure process; FIG. 3 depicts an improved flash memory erasure process; FIG. 4 depicts a nominal erasure voltage waveform; FIG. 5a depicts the spread of stored charge per cell as a function of a nominally applied erasure voltage; FIG. 5b depicts the spread of stored charge per cell as a function of an applied erasure voltage that is terminated early; FIG. 6 shows three phases of an erasure voltage waveform; FIGS. 7a and 7b depict the spread of stored charge per cell as a function of an applied erasure voltage for two early terminated erasure voltages; FIG. 8 shows a flow diagram for suspending an erasure iteration; FIG. 9 shows an SSD FIG. 10 shows a computing system. DETAILED DESCRIPTION Blocks of flash memory are commonly erased before being written to. FIG. 1 depicts a traditional erasure process. As observed in FIG. 1, the erasure of a single block entails applying an erasure voltage (VEV) to the block's storage cells and then checking (“verifying”) whether all the cells in the block have been properly erased and, if not, stepping up the erasure voltage, applying the increased erasure voltage to the cells (or, at least the cells that have not been properly erased) and re-verifying. The process continues until all cells in the block have been properly erased. Traditionally, the erase of a single block was performed with a single erase command that was passed, e.g., from an SSD controller to the NAND flash storage chip whose block is to be erased. As NAND flash storage cell densities increased, however, each block contained more and more storage cells. The erasure of an entire block therefore required the erasure of many more cells per erasure process. The increased number of cells per block resulted in a greater spread of cell responsivity to the applied erasure voltages (that is, as compared to earlier technologies, more cells per iteration were not properly erased) resulting in the execution of more erasure iterations to fully erase the block. The more erasure iterations translated to an undesired increased in the total time consumed erasing a block. The increased time needed to fully erase a block unfortunately caused the quality of service (QOS) to fall for other operations/commands (e.g., reads) that were forced to wait for the erasure to complete. Thus, to the users/threads/applications that were waiting for these operations/commands to be performed, the overall SSD appeared to be a slow mass storage device. U.S. Pat. No. 9,679,658 addressed this problem, as observed in FIG. 2, by breaking the erasure iterations into individual erasure command sequences. That is, for each erase iteration, the SSD controller sends an erase command 201 to the NAND flash memory device whose block is being erased. With each erasure iteration being performed as a separate erasure command, other commands, e.g., reads from other blocks of the same NAND memory chip targeted by the erasure could be inserted 202 in between the individual erasure iterations resulting in improved SSD speed from the perspective of all the users/threads/applications that use the SSD as a whole (only the user/thread/application whose block was being erased would observe decreased performance from prior generations, all other users/applications/threads of the SSD would observe improved performance). Unfortunately, with the further increase in NAND flash storage cell densities and/or the increasing demands placed on SSD devices in high performance data center applications, “big-data” applications and the like, the time consumed by a single erasure iteration is too large in view of the number of commands/operations that must wait for the single erasure iteration to complete. As such, FIG. 3 shows a further improvement in which each individual erasure iteration can be suspended by the SSD controller so that, e.g., commands/operations ta