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US-12620449-B2 - Adaptive GIDL voltage for erasing non-volatile memory

US12620449B2US 12620449 B2US12620449 B2US 12620449B2US-12620449-B2

Abstract

An apparatus is provided that includes a block of memory cells having a NAND string that includes a first select transistor, and a control circuit coupled to the block of memory cells. The control circuit is configured to perform an erase operation on the block of memory cells by determining a first count of a number of times that the block of memory cells previously has been programmed and erased, determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.

Inventors

  • Yihang Liu
  • Xiaochen Zhu
  • Lito De La Rama
  • Feng Gao

Assignees

  • SanDisk Technologies, Inc.

Dates

Publication Date
20260505
Application Date
20220831

Claims (12)

  1. 1 . An apparatus comprising: a block of memory cells comprising a NAND string that includes a first select transistor; and a control circuit coupled to the block of memory cells, the control circuit configured to perform an erase operation on the block of memory cells by: determining a first count of a number of times that the block of memory cells previously has been programmed and erased; determining based on the first count a first drain-to-gate voltage of the first select transistor, wherein the first drain-to-gate voltage is configured to cause the first select transistor to generate a first gate-induced drain leakage current, wherein the first drain-to-gate voltage adaptively changes in a step-wise manner based on the first count; and applying a first erase pulse to the first select transistor based on the determined first drain-to-gate voltage.
  2. 2 . The apparatus of claim 1 , wherein the first drain-to-gate voltage adaptively increases as a number of times that the block of memory cells previously has been programmed and erased increases.
  3. 3 . The apparatus of claim 1 , wherein the first drain-to-gate voltage comprises: an initial first drain-to-gate voltage when the first count is within a first range of values; and the initial first drain-to-gate voltage plus an offset when the first count is within a second range of values greater than the first range of values.
  4. 4 . The apparatus of claim 3 , wherein the offset is a fixed value.
  5. 5 . The apparatus of claim 1 , wherein the first drain-to-gate voltage is determined from a linear or non-linear equation based on the program-erase cycle count.
  6. 6 . The apparatus of claim 1 , wherein: the NAND string further includes a second select transistor; and the control circuit is further configured to perform the erase operation on the block of memory cells by: determining based on the first count a second drain-to-gate voltage of the second select transistor, wherein the second drain-to-gate voltage is configured to cause the second select transistor to generate a second gate-induced drain leakage current; and applying a second erase pulse to the second select transistor based on the determined second drain-to-gate voltage.
  7. 7 . The apparatus of claim 6 , wherein the second drain-to-gate voltage adaptively increases based on the first count.
  8. 8 . The apparatus of claim 6 , wherein the second drain-to-gate voltage adaptively increases as a number of times that the block of memory cells previously has been programmed and erased increases.
  9. 9 . The apparatus of claim 1 , wherein the control circuit is further configured to: perform an erase verify test on the block of memory cells; count a number of memory cells in the block that failed the erase verify test; determine that the count is less than or equal to a threshold number; and determine that the erase operation passed.
  10. 10 . The apparatus of claim 1 , wherein the control circuit is further configured to: perform an erase verify test on the block of memory cells; count a number of memory cells in the block that failed the erase verify test; determine that the count is greater than a threshold number; and determine that the erase operation failed.
  11. 11 . The apparatus of claim 1 determining the first drain-to-gate voltage is further based on a number of failed cells.
  12. 12 . The apparatus of claim 1 wherein the first drain-to-gate voltage further adaptively changes in a step-wise manner based on an offset value.

Description

BACKGROUND Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, servers, solid state drives, non-mobile computing devices and other devices. Semiconductor memory may comprise non-volatile memory or volatile memory. A non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a source of power (e.g., a battery). Examples of non-volatile memory include flash memory (e.g., NAND-type and NOR-type flash memory). Memory systems can be used to store data provided by a host device (or other client). However, various challenges are presented in operating such memory systems. In particular, as memory cells decrease in size and memory arrays increase in density, maintaining the integrity of data being stored becomes more challenging. BRIEF DESCRIPTION OF THE DRAWINGS Like-numbered elements refer to common components in the different figures. FIG. 1 is a block diagram depicting one embodiment of a memory system. FIG. 2 is a block diagram of one embodiment of a memory die. FIG. 3 is a perspective view of a portion of one embodiment of a three dimensional memory structure. FIG. 4A is a block diagram of a memory structure having two planes. FIG. 4B depicts a top view of a portion of a block of memory cells. FIG. 4C depicts a cross sectional view of a portion of a block of memory cells. FIG. 4D depicts a view of the select gate layers and word line layers. FIG. 4E is a cross sectional view of a memory hole of memory cells. FIG. 4F is a schematic of a plurality of NAND strings. FIG. 5 depicts threshold voltage distributions. FIG. 6 is a table describing one example of an assignment of data values to data states. FIGS. 7A-7E depict various threshold voltage distributions and describe a process for programming non-volatile memory. FIG. 8 is a flowchart describing an embodiment of a process for programming non-volatile memory. FIG. 9 depicts a word line voltage during programming and verify operations. FIG. 10 depicts a flowchart describing an embodiment of a process for erasing a population of memory cells. FIG. 11 depicts example erased threshold voltage distributions for a population of memory cells. FIG. 12A1 depicts a flowchart describing an embodiment of a process for erasing a population of memory cells. FIG. 12A2 depicts a table of program-erase cycle count values and corresponding adaptive GIDL voltage values. FIG. 12B depicts a flowchart describing an embodiment of another process for erasing a population of memory cells. FIG. 12C depicts a flowchart describing an embodiment of still another process for erasing a population of memory cells. DETAILED DESCRIPTION A 3D stacked non-volatile memory device can be arranged in multiple blocks, where typically an erase operation is performed one block at a time. An erase operation can include multiple erase-verify iterations which are performed until an erase-verify condition is met for the block, at which point the erase operation ends. In one approach, the memory device includes NAND strings which have a drain-side select gate (SGD) on one end and a source-side select gate (SGS) on the other end. The select gates play an important role in an erase operation because they are used to generate a sufficient amount of gate-induced drain leakage (GIDL) current to boost the NAND string channel. Boosting the channel creates a large channel-to-gate voltage which drives holes into the charge trapping layers, reducing the threshold voltage of each memory cell. Such a technique is referred to herein as “GIDL Erase.” In one approach, erase pulses are applied to one or both of the SGD and SGS of a NAND string to provide a drain-to-gate voltage of a sufficiently high magnitude (referred to herein as a GIDL voltage that the select transistor generates a GIDL current. However, the amount of GIDL current generated for a given GIDL voltage (referred to herein as “GIDL current efficiency”) decreases over the lifetime of a memory cell or group of memory cells. As GIDL current efficiency decreases, channel boosting decreases and corresponding threshold voltage reduction decreases. Technology is described for providing an adaptive GIDL voltage for erase operations on an erase block of non-volatile memory cells. In an embodiment, the value of the adaptive GIDL voltage is determined based on the number of program-erase cycles for the erase block. In an embodiment, the adaptive GIDL voltage increases as the number of program-erase cycles for the erase block increases. In another embodiment, the value of the adaptive GIDL voltage is determined based on the number of erase-verify loops used to erase the erase block. In an embodiment, the adaptive GIDL voltage increases as the number of erase-verify loops increases. Without wanting to be bound by any particular theory, it is believed that increasing the adaptiv