US-12620450-B2 - Aborted operation detection for nonvolatile memory with non-uniform erase

Abstract

An apparatus includes one or more control circuits that are configured to connect to a plurality of nonvolatile memory cells. The one or more control circuits are configured to detect a first boundary between written and unwritten portions of an open block and, in response to detecting the first boundary, check for a second boundary between written and unwritten portions of the open block in order to determine if the open block was subject to a non-uniform erase operation.

Inventors

• Huiwen Xu
• Deepanshu Dutta
• Ken Oowada
• Bo Lei
• Ravi J. Kumar
• Sujjatul Islam
• Xue Pitner

Assignees

• SanDisk Technologies, Inc.

Dates

Publication Date

20260505

Application Date

20230807

Claims (20)

1. 1 . An apparatus comprising: one or more control circuits configured to connect to a plurality of nonvolatile memory cells that are arranged in blocks, the one or more control circuits are configured to: detect a first boundary between written and unwritten portions of an open block and in response to detecting the first boundary to check for a second boundary between written and unwritten portions of the open block to determine if the open block is partially-erased by an aborted non-uniform erase operation, the non-uniform erase operation causes different nonvolatile memory cells of the block to be erased at different times such that the aborted non-uniform erase operation leaves written and unwritten portions.
2. 2 . The apparatus of claim 1 , wherein the one or more control circuits are configured to detect the first boundary by performing a binary search of word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified.
3. 3 . The apparatus of claim 2 , wherein the one or more control circuits are configured to check for the second boundary by reading a test word line that is a predetermined offset from a detected written word line.
4. 4 . The apparatus of claim 3 , wherein the non-uniform erase operation is an odd-even erase operation that separately erases odd word lines and even word lines and the test word line is immediately adjacent to the detected written word line.
5. 5 . The apparatus of claim 4 , wherein the one or more control circuits are configured to prepare the open block for erase without copying data from the open block in response to determining that the test word line is erased.
6. 6 . The apparatus of claim 1 , wherein the one or more control circuits are further configured to find a location of the first boundary in response to finding no second boundary between written and unwritten portions of the open block is found.
7. 7 . The apparatus of claim 6 , wherein the one or more control circuits are further configured to copy data on a written side of the first boundary from the open block to another block if no second boundary between written and unwritten portions of the open block is found.
8. 8 . The apparatus of claim 1 , wherein the one or more control circuits are configured to prepare the open block for erase without copying data from the open block in response to determining that the open block was subject to a non-uniform erase operation.
9. 9 . The apparatus of claim 1 , wherein the one or more control circuits are located on a control die that is configured to be connected to a memory die that includes the plurality of nonvolatile memory cells.
10. 10 . A method comprising: identifying a plurality of open blocks of a nonvolatile memory; detecting a first boundary between written and unwritten portions of each open block of the plurality of open blocks; subsequently, in response to detecting the first boundary between the written and unwritten portions of each open block, checking for a second boundary between written and unwritten portions of each open block to determine if the open block was subject to an aborted non-uniform erase operation; in response to finding the second boundary in a first open block, identifying the first open block as partially erased by an aborted non-uniform erase operation and preparing the first open block for erase without copying data from the first open block; and in response to failing to find the second boundary in a second open block, identifying the second open block as partially written and copying data from the second open block.
11. 11 . The method of claim 10 , wherein detecting the first boundary includes performing a binary search of word lines of the open block until at least one written word line is identified and at least one unwritten word line is identified.
12. 12 . The method of claim 11 , wherein checking for the second boundary includes reading a test word line that is a predetermined offset from a detected written word line.
13. 13 . The method of claim 12 , wherein the non-uniform erase operation is an odd-even erase operation that separately erases odd word lines and even word lines and the test word line is immediately adjacent to the detected written word line.
14. 14 . The method of claim 13 , further comprising preparing the open block for erase without copying data from the open block in response to determining that the test word line is erased.
15. 15 . The method of claim 10 , further comprising finding a location of the first boundary in response to finding no second boundary between written and unwritten portions of the open block.
16. 16 . The method of claim 15 , further comprising copying data on a written side of the first boundary from the open block to another block in response to finding no second boundary between written and unwritten portions of the open block.
17. 17 . The method of claim 11 , further comprising preparing the open block for erase without copying data from the open block in response to determining that the open block was subject to a non-uniform erase operation.
18. 18 . A data storage system comprising: a plurality of nonvolatile memory cells arranged in blocks; and means for detecting a first boundary between written and unwritten portions of an open block and in response to detecting the first boundary checking for a second boundary between written and unwritten portions of the open block to determine if the open block was subject to a non-uniform erase operation to erase different nonvolatile memory cells of the block at different times such that an aborted non-uniform erase operation leaves written and unwritten portions in the block.
19. 19 . The data storage system of claim 18 , wherein the non-uniform erase operation is an odd-even erase operation that separately erases odd word lines and even word lines and checking for the second boundary between written and unwritten portions includes checking a test word line located immediately adjacent to a word line determined as written.
20. 20 . The data storage system of claim 18 , wherein the plurality of nonvolatile memory cells are located on a memory die and the means for detecting the first boundary is located on a control die connected to the memory die.

Description

CLAIM OF PRIORITY The present application claims priority from U.S. Provisional Patent Application No. 63/509,134, entitled “ABORTED OPERATION DETECTION FOR NONVOLATILE MEMORY WITH NON-UNIFORM ERASE,” by Xu et al., filed Jun. 20, 2023, incorporated by reference herein in its entirety. BACKGROUND Semiconductor memory is widely used in various electronic devices such as cellular telephones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices and data servers. Semiconductor memory may comprise nonvolatile memory or volatile memory. A nonvolatile memory allows information to be stored and retained even when the nonvolatile memory is not connected to a source of power (e.g., a battery). Examples of nonvolatile memory include flash memory (e.g., NAND-type and NOR-type flash memory), Electrically Erasable Programmable Read-Only Memory (EEPROM), and others. Some memory cells store information by storing a charge in a charge storage region. Other memory cells store information using other techniques, such as by the resistance of the memory cell. Some memories store one bit per cell using two data states (Single Level Cell or SLC) while others store more than one bit per cell using more than two data states (Multi Level Cell or MLC, which may store two bits per cell). Storing four bits per cell may use sixteen data states may (Quad Level Cell or QLC). When a memory system is deployed in or connected to an electronic device (the host), the memory system can be used to store data and read data. For example, data may be stored in response to a program (write) command. Data may be read in response to a read command that specifies the data to be read. Data may be erased in response to an erase command. In some cases, an operation (e.g., write or erase) may be ongoing when a memory system loses power. When power returns, it may be difficult to determine the state of the memory system (e.g., some data may be partially written or partially erased). BRIEF DESCRIPTION OF THE DRAWINGS Like-numbered elements refer to common components in the different Figures. FIG. 1A is a block diagram of one embodiment of a memory system connected to a host. FIG. 1B is a block diagram of one embodiment of a Front-End Processor Circuit. In some embodiments, the Front-End Processor Circuit is part of a Controller. FIG. 1C is a block diagram of one embodiment of a Back End Processor Circuit. In some embodiments, the Back End Processor Circuit is part of a Controller. FIG. 1D is a block diagram of one embodiment of a memory package. FIG. 2A is a functional block diagram of an embodiment of a memory die. FIG. 2B is a functional block diagram of an embodiment of an integrated memory assembly. FIG. 3 is a perspective view of a portion of one embodiment of a monolithic three-dimensional memory structure. FIG. 4A is a block diagram of a memory structure having two planes. FIG. 4B depicts a top view of a portion of a block of memory cells. FIG. 4C depicts a cross sectional view of a portion of a block of memory cells. FIG. 5 shows an example of a sense block. FIG. 6 shows an example of programming multiple data states of nonvolatile memory cells. FIG. 7 shows an example of erasing nonvolatile memory cells. FIGS. 8A-F show examples of erase schemes. FIGS. 9A-D show examples of different conditions of a block. FIGS. 10A-B show examples of a binary search for a boundary in a block. FIGS. 11A-B show examples of determining a condition of a block. FIGS. 12A-B show examples of determining a condition of a block. FIG. 13 shows an example of a method that includes checking for a second boundary in a block. FIG. 14 shows an example of a method that includes checking for a second boundary in a block. FIG. 15 shows an example of a method that includes determining if a test word line is erased. DETAILED DESCRIPTION Techniques are disclosed herein to enable a memory system to efficiently determine the condition of a block (e.g., after an unexpected loss of power when the condition of a block may be unknown). Some memory systems use non-uniform erase, for example, separately erasing memory cells of odd and even word lines (odd-even erase), which may result in a pattern of written and unwritten portions in a block. Such patterns may result in misidentifying blocks as partially written with valid data (e.g., misidentified as write abort blocks) when they contain no valid data (e.g., are erase abort blocks). Misidentification may result in inappropriate treatment of such blocks (e.g., attempting to copy data from a block that contains no valid data) which may impact operations of a memory system. A scheme to accurately and efficiently determine the condition of a block includes detecting a first boundary between written and unwritten portions (e.g., finding at least one written word line and at least one unwritten word line). In response to detecting the first boundary, the block may be checked for a