US-12620451-B2 - Memory system, debugging device, debugging method of memory system, and method of operating memory system

US12620451B2US 12620451 B2US12620451 B2US 12620451B2US-12620451-B2

Abstract

A memory system includes: a memory device configured to store a plurality of data items; a scan chain configured to receive the plurality of data items and to generate scan-out data for the plurality of data items; and a controller configured to replace the scan-out data with replaced data. The scan chain is further configured to receive the replaced data from the controller.

Inventors

Bumju Kim
Jaecheon Kim

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240308
Priority Date: 20230309

Claims (19)

1 . A memory system comprising: a memory device configured to store a plurality of data items; a processor configured to generate a replacement command based on a determination that an error exists in at least one data item of the plurality of data items; a controller configured to receive the replacement command from the processor and to replace a first data value of the at least one data item of the plurality of data items with a second data value based on the replacement command; and a scan chain configured to receive the plurality of data items including the second data value from the controller and to generate scan-out data corresponding to the plurality of data items including the second data value, wherein the first data value of the at least one data item comprises a first bit value, wherein the second data value comprises a second bit value, and wherein the replacement command includes a command for inverting the first bit value to the second bit value.
2 . The memory system of claim 1 , wherein the controller comprises a serializer configured to convert at least one replaced data of the plurality of data items into serial data sequentially output in a unit of a bit.
3 . The memory system of claim 2 , wherein the scan chain is configured to receive the serial data.
4 . The memory system of claim 1 , wherein the controller further comprises a deserializer configured to convert the scan-out data into parallel data to be received in parallel in a unit of multi-bits.
5 . The memory system of claim 1 , wherein the scan chain is configured to receive a scan chain enable signal, based on the plurality of data items received by the scan chain.
6 . The memory system of claim 5 , wherein the scan chain is configured to stop receiving the scan chain enable signal, based on a condition that the scan chain terminates a reception of the plurality of data items.
7 . The memory system of claim 1 , further comprising a joint test action group (JTAG) interface circuit, wherein, based on the error existing in the at least one data item of the plurality of data items, the at least one data item of the plurality of data items is read through the JTAG interface circuit.
8 . The memory system of claim 1 , wherein the controller is further configured to receive second scan-out data from the scan chain and store the second scan-out data as the plurality of data items in the memory device before the processor generates the replacement command.
9 . A debugging method of a memory system for detecting an error in at least one data item of a plurality of data items stored in a memory device of the memory system, the debugging method comprising: generating, by a processor, a replacement command for a first data value of the at least one data item of the plurality of data items based on a determination of the error existing in the at least one data item of the plurality of data items; receiving, by a controller, the replacement command from the processor; replacing, by the controller, the first data value of the at least one data item of the plurality of data items with a second data value based on the replacement command; receiving, by a scan chain, the plurality of data items including the second data value; and generating, by the scan chain, scan-out data corresponding to the plurality of data items including the second data value, wherein the first data value of the at least one data item comprises a first bit value, wherein the second data value comprises a second bit value, and wherein the replacement command includes a command for inverting the first bit value to the second bit value.
10 . The debugging method of claim 9 , further comprising converting the second data value into data in a form of a single bit.
11 . The debugging method of claim 10 , wherein the generating, by the scan chain, the scan-out data comprises scanning the second data value, and wherein, in the scanning of the second data value, the converted second data value in the form of the single bit is received.
12 . The debugging method of claim 9 , further comprising converting an output of the scan chain into another data in a form of multi-bits.
13 . The debugging method of claim 9 , further comprises receiving a scan chain enable signal, based on the second data value that is an input.
14 . The debugging method of claim 13 , wherein the generating, by the scan chain, the scan-out data comprises scanning the second data value, and wherein, in the receiving of the scan chain enable signal and the scanning of the second data value, a scan chain disable signal is received, based on a condition that the input is terminated.
15 . The debugging method of claim 9 , further comprising reading the at least one data item of the plurality of data items through a joint test action group (JTAG) interface circuit, based on the error existing in the at least one data item of the plurality of data items.
16 . The debugging method of claim 9 , further comprising: receiving, by the controller, second scan-out data from the scan chain; and storing, by the controller, the second scan-out data as the plurality of data items in the memory device before the processor generates the replacement command.
17 . A debugging device comprising: a processor configured to generate a replacement command based on a determination that an error exists in at least one data item of a plurality of data items stored in a memory; a controller configured to receive the replacement command from the processor and to replace a first data value of the at least one item of the plurality of data items with a second data value; and a scan chain configured to receive, from the controller, the plurality of data items including the second data value and to generate scan-out data corresponding to the plurality of data items including the second data value, wherein the first data value of the at least one data item comprises a first bit value, wherein the second data value comprises a second bit value, and wherein the replacement command includes a command for inverting the first bit value to the second bit value.
18 . The debugging device of claim 17 , wherein the controller comprises a serializer configured to convert the second data value into serial data sequentially output in a unit of a single bit.
19 . The debugging device of claim 17 , wherein the controller is further configured to receive second scan-out data from the scan chain and store the second scan-out data as the plurality of data items in the memory before the processor generates the replacement command.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is based on and claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2023-0031364, filed on Mar. 9, 2023, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND 1. Field The disclosure relates to a memory system, a debugging device, a debugging method of a memory system, and a method of operating a memory system, and more particularly, to a debugging device and method for detecting an error in data by replacing a data value with another data value based on an error existing in at least one of a plurality of data items. 2. Description of Relate Art In a conventional scan-dump method of a memory system, the same sequence as a previous sequence may be repeatedly used for debugging when the same scenario is tested after values loaded in a scan chain are shifted out. In addition, in a conventional debugging method of the memory system, an error may be detected by extracting data items loaded in the scan chain to the outside, or a flip-flop included in the scan chain may be reconstructed by providing an output of the scan chain to an input of the scan chain. However, the conventional scan-dump method and the conventional debugging method may take a lot of time and has a problem in that a plurality of flip-flops may not be reconstructed at once. SUMMARY Provided are a method and a memory system performing a debugging operation by replacing a data value stored in a memory device and inputting the replaced data value to a scan chain based on an error existing in data having the data value. Provided are a method and a memory system capable of detecting an error in data by replacing only a part or a data value in the data, which is suspicious of having an error, and thus, reducing time required for detecting the error. According to one aspect of the disclosure, a memory device configured to store a plurality of data items; a scan chain configured to receive the plurality of data items and to generate scan-out data for the plurality of data items; and a controller configured to replace the scan-out data with replaced data. The scan chain is further configured to receive the replaced data from the controller. According to another aspect of the disclosure, a debugging method of a memory system for detecting an error in at least one data item of a plurality of data items, includes: receiving the plurality of data items; generating scan-out data for the plurality of data items; and replacing the scan-out data with replaced data, wherein the generating of the scan-out data includes: generating a replacement command for a data value of at least one data item of the plurality of data items; replacing the data value of the at least one data item with replaced data value, based on the replacement command; scanning the replaced data value; and detecting an error in at least one data item of the plurality of data items, based on the replaced data value. According to another aspect of the disclosure, a debugging device includes: a scan chain configured to receive a plurality of data items from a memory device and to generate scan-out data for the plurality of data items; and a controller configured to replace the scan-out data with replaced data, wherein the scan chain is configured to receive the replaced data from the controller. According to another aspect of the disclosure, a method of operating a memory system for detecting an error in at least one data item of a plurality of data items, includes: receiving the plurality of data items and generating scan-out data for the plurality of data items; and replacing the scan-out data with replaced data, wherein the generating of the scan-out data includes: generating a replacement command for a data value of at least one data item of the plurality of data items; replacing the data value of the at least one data item with another data value, based on the replacement command; scanning the replaced another data value; and detecting an error in the at least one data item of the plurality of data items based on the replaced another data value. BRIEF DESCRIPTION OF DRAWINGS Embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings in which: FIG. 1 illustrates a block diagram of a memory system according to an embodiment; FIG. 2 illustrates a debugging device according to an embodiment; FIG. 3 illustrates a memory controller of a memory system according to an embodiment; FIG. 4 illustrates a scan chain of a memory system according to an embodiment; FIG. 5 illustrates generation of a clock control signal in a memory system according to an embodiment; FIGS. 6 and 7 illustrate embodiments in which data is replaced; FIG. 8 illustrates a clock timing diagram according to a debugging method according to an embodiment; FIG. 9 illustrates a debugging method according to