US-12620534-B2 - Film capacitor on a glass substrate

US12620534B2US 12620534 B2US12620534 B2US 12620534B2US-12620534-B2

Abstract

Embodiments herein relate to systems, apparatuses, or processes directed to packages that include one or more glass cores that have thin film capacitors on one or more sides of the one or more glass cores. The film capacitors may be formed in-situ on the glass cores during substrate manufacturing. Other embodiments may be described and/or claimed.

Inventors

Chong Zhang
Cheng Xu
Junnan Zhao
Ying Wang
Meizi Jiao

Assignees

INTEL CORPORATION

Dates

Publication Date: 20260505
Application Date: 20211221

Claims (20)

1 . A capacitor comprising: a layer of glass having a first side and a second side opposite the first side; a first layer of metal on the first side of the layer of glass; a layer of capacitor film on the first layer of metal; a second layer of metal on the capacitor film, wherein the first layer of metal and the second layer of metal are electrically isolated from each other; a first conductive via extending through the layer of glass, the first conductive via coupled to the second layer of metal by a first routing layer; and a second conductive via extending through the layer of glass, the second conductive via coupled to the first layer of metal by a second routing layer, the second routing layer in a same horizontal plane as the first routing layer.
2 . The capacitor of claim 1 , further comprising: an opening extending through the second layer of metal and the layer of capacitor film; and a metal contact within the opening, electrically and physically coupled with the first layer of metal and extending above the second layer of metal, wherein the metal contact and the second layer of metal are electrically isolated from each other.
3 . The capacitor of claim 2 , further including a dielectric within the opening and at least partially surrounding the metal contact.
4 . The capacitor of claim 2 , wherein the metal contact is a metal via.
5 . The capacitor of claim 1 , wherein the layer of capacitor film is a first layer of capacitor film; and further comprising: a second layer of capacitor film on the second layer of metal; a third layer of metal on the second layer of capacitor film; and wherein the first layer of metal and the third layer of metal are electrically coupled, and wherein the third layer of metal and the second layer of metal are electrically isolated from each other.
6 . The capacitor of claim 5 , further comprising: a third layer of capacitor film on the third layer of metal; a fourth layer of metal on the third layer of capacitor film; and wherein the second layer of metal and the fourth layer of metal are electrically coupled, and wherein the fourth layer of metal and the third layer of metal are electrically isolated from each other.
7 . The capacitor of claim 1 , wherein the first layer of metal and the second layer of metal include copper.
8 . The capacitor of claim 1 , wherein the capacitor film includes a selected one or more of barium, titanium, and/or oxygen.
9 . The capacitor of claim 1 , wherein the opening is at an edge of the layer of capacitor film and the second layer of metal.
10 . The capacitor claim 1 , wherein the first layer of metal is electrically coupled with a Vdd and the second layer of metal is electrically coupled with a Vss.
11 . The capacitor of claim 1 , wherein at least a portion of the first layer of metal is within a recess in the first side of the layer of glass.
12 . The capacitor of claim 1 , wherein a thickness of the capacitor film is under 1 micrometer.
13 . The capacitor of claim 1 , wherein the first layer of metal, the layer of capacitor film, and the second layer of metal are substantially planar.
14 . A method comprising: providing a glass core having a first side and a second side opposite the first side; forming a first layer of metal on the first side of the glass core; forming a layer of capacitor film on the first layer of metal; forming a second layer of metal on the layer of capacitor film, wherein the first layer of metal and the second layer of metal are electrically isolated from each other; forming a first conductive via extending through the layer of glass, the first conductive via coupled to the second layer of metal by a first routing layer; and forming a second conductive via extending through the layer of glass, the second conductive via coupled to the first layer of metal by a second routing layer, the second routing layer in a same horizontal plane as the first routing layer.
15 . The method of claim 14 , further comprising: forming an opening extending through the second layer of metal and through the layer of capacitor film; and forming a metal contact within the opening and electrically and physically coupled with the first layer of metal and extending above the second layer of metal, wherein the metal contact and second layer of metal are electrically isolated from each other.
16 . The method of claim 15 , further including placing a dielectric within the opening and at least partially surrounding the metal contact.
17 . The method of claim 15 , wherein forming the metal contact further includes: placing a dielectric within the formed opening; and forming a metal via within the dielectric, the metal via physically and electrically coupled with the first layer of metal and electrically isolated from the second layer of metal.
18 . The method of claim 14 , wherein the first layer of metal and the second layer of metal include copper.
19 . The method of claim 14 , wherein the capacitor film includes a selected one or more of barium, titanium, and/or oxygen.
20 . A package comprising: a substrate comprising: a glass core having a first side and a second side opposite the first side; a first layer of metal on the first side of the glass core; a layer of capacitor film on the first layer of metal; a second layer of metal on the layer of capacitor film, wherein the first layer of metal and the second layer of metal are electrically isolated from each other; a first conductive via extending through the glass core, the first conductive via coupled to the second layer of metal by a first routing layer; a second conductive via extending through the glass core, the second conductive via coupled to the first layer of metal by a second routing layer, the second routing layer in a same horizontal plane as the first routing layer; an opening extending through the second layer of metal and through the layer of capacitor film to expose a surface of the first layer of metal; and a metal contact within the opening and electrically and physically coupled with the first layer of the metal and extending above the second layer of metal, wherein the metal contact and second layer of metal are electrically isolated from each other; and a die physically coupled with the first side of the glass core, wherein the die is electrically coupled with the metal contact and with the second layer of metal.

Description

FIELD Embodiments of the present disclosure generally relate to the field of package assemblies, and in particular to packages that include glass cores. BACKGROUND Continued reduction in the size of mobile electronic devices, such as smart phones and ultrabooks, is a driving force for reducing package sizes and increasing the quality of components within packages. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a side view cross section of a package with a glass core with a thin film capacitor on a side of the glass core, in accordance with various embodiments. FIG. 2 illustrates a side view cross section of a package with a glass core that includes a recess on a side of the glass core with a stacked multi-layer thin film capacitor within a part of the recess, in accordance with various embodiments. FIG. 3 illustrates a top view and a cross section side view of a package with a glass core with a thin film capacitor on a side of the glass core that is electrically coupled to through glass vias (TGV) filled with copper, in accordance with various embodiments. FIG. 4 illustrates several top views of various layer geometries of the thin film capacitor, in accordance with various embodiments. FIGS. 5A-5G illustrate stages in the manufacturing process for creating a thin film capacitor on a side of a glass core, in accordance with various embodiments. FIG. 6 illustrates multiple examples of laser-assisted etching of glass interconnects processes, in accordance with various embodiments. FIGS. 7A-7B schematically illustrate a top view of an example die in wafer form and in singulated form, and a cross section side view of a package assembly, in accordance with various embodiments. FIG. 8 illustrates an example of a process for creating a thin film capacitor on a glass substrate, in accordance with various embodiments. FIG. 9 schematically illustrates a computing device, in accordance with embodiments. DETAILED DESCRIPTION Embodiments of the present disclosure may generally relate to systems, apparatus, and/or processes directed to packages that include glass cores that have thin film capacitors coupled with one or more sides of the glass cores. In embodiments, these thin film capacitors may be formed in-situ on the glass cores during substrate manufacturing. In embodiments, these thin film capacitors may be layered on top of each other to create additional capacitance with a minimum increase of Z-height. In embodiments, thin film capacitors may be designed so that they are closer and have a shorter electrical routing path to a die that is attached to the glass core. The shorter electrical routing path may be significantly shorter than electrical routing paths of discrete capacitors, for example either land side capacitors (LSC) or die side capacitors (DSC). In embodiments, the thin film capacitors may include a first metal layer formed on a surface of the glass core, with a dielectric film on top of the first metal layer, and a second metal layer on top of the dielectric film. In legacy implementations, capacitors are typically implemented on a substrate interconnect and provide power delivery to dies, such as CPUs, coupled with the substrate interconnect. In these legacy implementations, DSCs and LSCs may be used. DSCs typically have smaller size because the front side of a legacy package does not have much space, and the power supplied is likely limited because the electrical connection is made horizontally through power traces. In legacy implementations, LSCs can occupy more space and are connected to CPU die through vertical stacked via connections. However, because LSCs are relatively far away from CPU die, these legacy implementations have reduced power delivery performance. In addition, with legacy implementations, external discreet capacitors may be expensive to purchase, and may provide challenges during manufacturing. For example, implementing capacitor materials in a package requires an annealing temperature that is much higher than the melting point of an organic substrate that may exist within a legacy package. In addition, legacy capacitors may be bulky and have a Z-height that constrains package design. In addition, many legacy components are attached at a back side of the substrate, which may be relatively far away from a CPU die on the other side of the substrate creating a longer electrical routing path. In embodiments described herein, the capacitor structures are embedded within the package on a glass core. As a result, Z-height constraints and form factor constraints are greatly reduced as compared to legacy implementations. In addition, the effect of high annealing temperatures for capacitor materials during manufacture of the package. Because a glass core instead of a legacy organic core is used, the glass core is far less likely to degrade or deform even at sintering temperatures. For example, a film dielectric that includes BaTiO3 may require temperatures around 900° C. during manufact