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US-12620783-B1 - Methods for 3D-integrating photonic chipsets by vertical assembly of lasers and passive components

US12620783B1US 12620783 B1US12620783 B1US 12620783B1US-12620783-B1

Abstract

A method for making a vertically arranged array of edge-emitting lasers comprises: obtaining semiconductor chips that are laser diodes or semiconductor optical amplifiers; coating each of the semiconductor chips with a thermally conductive dielectric material; bonding the semiconductor chips onto a carrier wafer, such that the semiconductor chips are vertically aligned; coating the semiconductor chips with an electroplating seed material; obtaining a body wafer having lithographically defined and passivated openings; positioning the body wafer and the carrier wafer to match the openings; electroplating a metal-containing material onto the seed material to fill open space; demounting the body wafer from the carrier wafer; etching excess material from the body wafer; and patterning metal regions in electrical contact with the semiconductor chips. A vertically arranged array of edge-emitting lasers is fabricated and is capable of emitting laser light parallel to the semiconductor chips and perpendicular to the plane of the body wafer.

Inventors

  • John Carlson
  • Travis AUTRY
  • Florian Herrault

Assignees

  • HRL LABORATORIES, LLC

Dates

Publication Date
20260505
Application Date
20230520

Claims (20)

  1. 1 . A method for making a vertically arranged array of edge-emitting lasers, said method comprising: (a) obtaining a plurality of semiconductor chips, wherein said semiconductor chips are laser diodes or semiconductor optical amplifiers; (b) coating each of said semiconductor chips on multiple sides with a thermally conductive dielectric material; (c) bonding said semiconductor chips onto a carrier wafer at selected locations, wherein said semiconductor chips are vertically aligned relative to a surface of said carrier wafer; (d) coating each of said semiconductor chips with an electroplating seed material; (e) obtaining a body wafer having lithographically defined and passivated openings within a plane of said body wafer; (f) positioning said body wafer and said carrier wafer to match said lithographically defined and passivated openings with said semiconductor chips; (g) electroplating a metal-containing material onto said electroplating seed material to fill open space between said semiconductor chips and said lithographically defined and passivated openings; (h) demounting said body wafer from said carrier wafer; (i) etching excess material, if any, from said body wafer; and (j) patterning a plurality of metal regions in electrical contact with said plurality of semiconductor chips, thereby generating a vertically arranged array of edge-emitting lasers that is capable of emitting laser light parallel to said semiconductor chips and perpendicular to said plane of said body wafer.
  2. 2 . The method of claim 1 , wherein said semiconductor chips are fabricated from a semiconductor selected from the group consisting of GaAs, InP, GaSb, GaN, InGaN, AlGaN, AlGaInP, GaInP, GaAlAs, InGaAs, InGaAsP, GaInAsSb, and combinations thereof.
  3. 3 . The method of claim 1 , wherein said semiconductor chips are capable of emitting or amplifying ultraviolet laser light, visible laser light, infrared laser light, or a combination thereof.
  4. 4 . The method of claim 1 , wherein said semiconductor chips are each configured to emit or amplify at a single light wavelength.
  5. 5 . The method of claim 1 , wherein said semiconductor chips are collectively configured to emit or amplify at multiple light wavelengths.
  6. 6 . The method of claim 1 , wherein said thermally conductive dielectric material is selected from the group consisting of aluminum nitride, boron nitride, tantalum oxide, beryllium oxide, aluminum oxide, and combinations thereof.
  7. 7 . The method of claim 1 , wherein step (b) comprises coating each of said semiconductor chips on five sides with said thermally conductive dielectric material.
  8. 8 . The method of claim 1 , wherein step (c) utilizes an adhesive for said bonding.
  9. 9 . The method of claim 8 , wherein said adhesive is selected from the group consisting of polyimide, cyanoacrylate, acrylic, polyepoxides, polyethylene, polystyrene, ceramics, benzocyclobutene, parylene, and combinations thereof.
  10. 10 . The method of claim 1 , wherein said body wafer is fabricated from a body-wafer material selected from the group consisting of silicon, silicon carbide, germanium, gallium nitride, aluminum nitride, gallium oxide, silica, alumina, and combinations thereof.
  11. 11 . The method of claim 1 , wherein said carrier wafer is fabricated from a carrier-wafer material selected from the group consisting of silicon, silicon carbide, germanium, gallium nitride, aluminum nitride, gallium oxide, silica, alumina, and combinations thereof.
  12. 12 . The method of claim 1 , wherein said electroplating seed material is selected from the group consisting of copper, ruthenium, molybdenum, cobalt, titanium, platinum, gold, silver, nickel, chromium, aluminum, tantalum nitride, and combinations thereof.
  13. 13 . The method of claim 1 , wherein step (d) comprises coating each of said semiconductor chips on five sides with said electroplating seed material.
  14. 14 . The method of claim 1 , wherein said lithographically defined and passivated openings are characterized by an average cavity length, and wherein said vertically arranged array of edge-emitting lasers is characterized by an average array pitch that is less than said average cavity length in at least one planar dimension.
  15. 15 . The method of claim 1 , wherein step (e) comprises obtaining a starting body wafer, etching said starting body wafer to create etched openings, and then passivating said etched openings to create said lithographically defined and passivated openings.
  16. 16 . The method of claim 15 , wherein said passivating utilizes (i) native oxidation of said etched openings, (ii) deposition of an oxide layer onto said etched openings, and/or (iii) deposition of a nitride layer onto said etched openings.
  17. 17 . The method of claim 1 , wherein said metal-containing material in step (g) is selected from the group consisting of copper, ruthenium, molybdenum, cobalt, titanium, gold, silver, nickel, aluminum, indium, tin, and combinations thereof.
  18. 18 . The method of claim 1 , wherein said metal-containing material is chemically the same as said electroplating seed material.
  19. 19 . The method of claim 1 , wherein said metal-containing material is chemically different than said electroplating seed material.
  20. 20 . The method of claim 1 , wherein step (i) comprises etching excess thermally conductive dielectric material.

Description

FIELD OF THE INVENTION The present invention generally relates to integrated photonic systems, and methods of making and using integrated photonic systems. BACKGROUND OF THE INVENTION A laser is a device that emits light through a process of optical amplification based on the stimulated emission of electromagnetic radiation. In 1960, researchers at Hughes Research Laboratories (now HRL Laboratories, LLC) proved that the fundamental laser concept could actually work. See U.S. Pat. No. 3,353,115, entitled “Ruby laser systems” issued to Theodore Maiman on Nov. 14, 1967. Since then, researchers at HRL Laboratories have continued to investigate and exploit the enormous advantages of optics and optoelectronics. Lasers are ubiquitous in today's society. Lasers are used in military and law-enforcement devices for marking targets and measuring range and speed, fiber-optic communication, free-space optical communication, advanced signaling systems, semiconducting chip manufacturing (photolithography), optical disc drives, laser printers, DNA sequencing instruments, laser surgery, and cutting and welding materials, to name just a few applications. A vertical-cavity surface-emitting laser, or VCSEL, is a type of semiconductor laser diode with laser beam emission perpendicular from the top surface. A VCSEL contrasts with an edge-emitting laser, or EEL (also known as an in-plane laser) which emits light from surfaces formed by cleaving an individual chip out of a wafer. The VCSEL structure is markedly different than the EEL structure. Verticality is desirable for lasers since verticality allows light to escape out of the plane (perpendicular to the plane) of the semiconductor chip and be sent into a fiber or other system. While VCSELs may be vertical, they suffer from numerous performance limitations that are not present in EELs. A VCSEL has lower optical output power, narrower choice of wavelength range (typically just 770-905 nm), much broader spectral linewidth, and multi-mode beam emission. Additionally, a VCSEL is not easily extended with external cavity elements or spectral tuning structures. These limitations inherently follow from the structure utilized to cause the VCSEL to emit vertically. As a result of these limitations, and notwithstanding the desire for vertical out-of-plane laser emission, VCSELs are not used in high-power applications, long-range LIDAR, high-performance or coherent sources, visible/UV/mid-IR lasers, photonic integrated circuits, quantum or nonlinear pump applications, long-haul telecommunications at the C-band, or in defense applications. There have been attempts to take in-plane light from an EEL and try to constrain the light to go out-of-plane, with efforts to balance the corresponding losses that occur. Techniques to mount or couple the EEL for light extraction represent an appreciable segment of the optics and microfabrication community. In view of the aforementioned needs in the art, there is a strong desire for vertical out-of-plane laser emission from a compact and chip-scale source that can illuminate, detect, and/or interrogate objects outside of the plane of the chip. The vertical out-of-plane laser device preferably has small size, weight, and power, as well as high power emission at a given wavelength. SUMMARY OF THE INVENTION The present invention addresses the aforementioned needs in the art, as will now be summarized and then further described in detail below. In some variations, the invention provides a method for making a vertically arranged array of edge-emitting lasers, the method comprising: (a) obtaining a plurality of semiconductor chips, wherein the semiconductor chips are laser diodes or semiconductor optical amplifiers;(b) coating each of the semiconductor chips on multiple sides with a thermally conductive dielectric material;(c) bonding the semiconductor chips onto a carrier wafer at selected locations, wherein the semiconductor chips are vertically aligned relative to a surface of the carrier wafer;(d) coating each of the semiconductor chips with an electroplating seed material;(e) obtaining a body wafer having lithographically defined and passivated openings within a plane of the body wafer;(f) positioning the body wafer and the carrier wafer to match the lithographically defined and passivated openings with the semiconductor chips;(g) electroplating a metal-containing material onto the electroplating seed material to fill open space between the semiconductor chips and the lithographically defined and passivated openings;(h) demounting the body wafer from the carrier wafer;(i) etching excess material, if any, from the body wafer; and(j) patterning a plurality of metal regions in electrical contact with the plurality of semiconductor chips,thereby generating a vertically arranged array of edge-emitting lasers that is capable of emitting laser light parallel to the semiconductor chips and perpendicular to the plane of the body wafer. In some embodiments, the se