US-12620802-B2 - Semiconductor device structure and method of manufacturing the same

Abstract

Semiconductor device structures and methods for manufacturing the same are provided. The semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first transistor and a clamping device. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first transistor is disposed on the second nitride semiconductor layer. The first transistor includes a first control electrode, a first current electrode and a second current electrode. The clamping device is disposed on the second nitride semiconductor layer and electrically coupled with the first transistor. The clamping device includes a second transistor and a third transistor electrically coupled with the second transistor. The clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor.

Inventors

• Chang Chen
• Xiaoming Liu
• Xinyu Li

Assignees

• Innoscience (suzhou) Semiconductor Co., Ltd.

Dates

Publication Date

20260505

Application Date

20221115

Claims (20)

1. 1 . A semiconductor device structure, comprising: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first transistor disposed on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; a clamping device disposed on the second nitride semiconductor layer and electrically coupled with the first transistor, wherein the clamping device comprises a second transistor and a third transistor electrically coupled with the second transistor, and the clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor; and a third nitride semiconductor layer doped with impurities and disposed between the first control electrode and the second nitride semiconductor layer.
2. 2 . The semiconductor device structure of claim 1 , wherein the second transistor comprises a second control electrode and a third current electrode, the third transistor comprises a third control electrode and a fourth current electrode, and a first potential midpoint is electrically coupled with the first control electrode, the third current electrode, and the fourth current electrode.
3. 3 . The semiconductor device structure of claim 2 , wherein a first dimension of the first control electrode is different from a second dimension of the second control electrode.
4. 4 . The semiconductor device structure of claim 2 , wherein the first dimension of the first control electrode is greater than the second dimension of the second control electrode.
5. 5 . The semiconductor device structure of claim 2 , wherein a first distance between the first control electrode and the first current electrode of the first transistor is different from a second distance between the second control electrode and the third current electrode of the second transistor.
6. 6 . The semiconductor device structure of claim 5 , wherein the first distance between the first control electrode and the first current electrode of the first transistor is greater than the second distance between the second control electrode and the third current electrode.
7. 7 . The semiconductor device structure of claim 2 , wherein the clamping device further comprises a fourth transistor and a fifth transistor, the fourth transistor comprises a fourth control electrode, the fifth transistor comprises a fifth control electrode, and the first potential midpoint is electrically coupled with the fourth control electrode and the fifth control electrode.
8. 8 . The semiconductor device structure of claim 7 , wherein the fourth transistor comprises a seventh current electrode, and a second potential midpoint is electrically coupled with the seventh current electrode of the fourth transistor and the second current electrode of the first transistor.
9. 9 . The semiconductor device structure of claim 7 , wherein the fourth transistor comprises an eighth current electrode electrically coupled with the second control electrode of the second transistor.
10. 10 . The semiconductor device structure of claim 7 , wherein the fifth transistor comprises a ninth current electrode, and a third potential midpoint is electrically coupled with the nine current electrode of the fifth transistor and the first current electrode of the first transistor.
11. 11 . The semiconductor device structure of claim 7 , wherein the fifth transistor comprises a tenth current electrode electrically coupled with the third control electrode of the third transistor.
12. 12 . The semiconductor device structure of claim 7 , wherein the first dimension of the first control electrode is different from a third dimension of the fourth control electrode.
13. 13 . The semiconductor device structure of claim 7 , wherein the first dimension of the first control electrode is greater than the third dimension of the fourth control electrode.
14. 14 . The semiconductor device structure of claim 1 , further comprising: a capacitor electrically connected to the second current electrode.
15. 15 . A method of manufacturing a semiconductor device structure, comprising: providing a substrate; forming a first nitride semiconductor layer on the substrate; forming a second nitride semiconductor layer on the first nitride semiconductor layer; forming a first transistor on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; forming a clamping device on the second nitride semiconductor layer, wherein the clamping device comprises a second transistor and a third transistor electrically coupled with the second transistor, and the clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor; and forming a third nitride semiconductor layer doped with impurities, wherein the third nitride semiconductor layer is located between the first control electrode and the second nitride semiconductor layer.
16. 16 . The method of claim 15 , further comprising: forming a capacitor electrically connected to the first transistor.
17. 17 . The method of claim 15 , wherein the second transistor comprises a second control electrode and a third current electrode, the third transistor comprises a third control electrode and a fourth current electrode, and a first potential midpoint is electrically coupled with the first control electrode, the third current electrode, and the fourth electrode.
18. 18 . The method of claim 15 , wherein a first dimension of the first control electrode is different from a second dimension of the second control electrode.
19. 19 . A semiconductor device structure, comprising: a substrate; a first nitride semiconductor layer disposed on the substrate; a second nitride semiconductor layer disposed on the first nitride semiconductor layer; a first transistor disposed on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; and a clamping device disposed on the second nitride semiconductor layer, wherein the clamping device comprises a second transistor and a third transistor, the second transistor comprises a second control electrode, a third current electrode, and fourth current electrode, the third transistor comprises a third control electrode and a fifth current electrode, and wherein the third current electrode of the second transistor is coupled with the third control electrode of the third transistor, a first potential midpoint is connected to the fifth current electrode of the third transistor and the first current electrode of the first transistor, and a second potential midpoint is connected to the fourth current electrode of the second transistor and the second current electrode of the first transistor.
20. 20 . The semiconductor device structure of claim 19 , wherein a third potential midpoint is connected to the first control electrode of the first transistor and the second control electrode of the second transistor.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a 371 of international application of PCT application serial no. PCT/CN2022/131892, filed on Nov. 15, 2022. The entirety of the above mentioned patent application is hereby incorporated by reference herein and made a part of this specification. BACKGROUND 1. Field of the Disclosure The present disclosure relates to a semiconductor device structure and more particularly to a semiconductor device structure including a clamping device. 2. Description of Related Art Components including direct bandgap semiconductors, such as semiconductor components including group III-V materials or group III-V compounds (Category: III-V compounds) can operate or work under a variety of conditions or in a variety of environments (e.g., at different voltages and frequencies). The semiconductor components may include a heterojunction bipolar transistor (HBT), a heterojunction field effect transistor (HFET), a high-electron-mobility transistor (HEMT), a modulation-doped FET (MODFET) and the like. SUMMARY According to some embodiments of the present disclosure, a semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first transistor and a clamping device. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first transistor is disposed on the second nitride semiconductor layer. The first transistor includes a first control electrode, a first current electrode and a second current electrode. The clamping device is disposed on the second nitride semiconductor layer and electrically coupled with the first transistor. The clamping device includes a second transistor and a third transistor electrically coupled with the second transistor. The clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor. According to some embodiments of the present disclosure, a method of manufacturing a semiconductor device structure includes: providing a substrate; forming a first nitride semiconductor layer on the substrate; forming a second nitride semiconductor layer on the first nitride semiconductor layer; forming a first transistor on the second nitride semiconductor layer, wherein the first transistor comprises a first control electrode, a first current electrode and a second current electrode; and forming a clamping device on the second nitride semiconductor layer. The clamping device includes a second transistor and a third transistor electrically coupled with the second transistor. The clamping device is electrically coupled with the first current electrode and the second current electrode of the first transistor. According to some embodiments of the present disclosure, a semiconductor device structure includes a substrate, a first nitride semiconductor layer, a second nitride semiconductor layer, a first transistor and a clamping device. The first nitride semiconductor layer is disposed on the substrate. The second nitride semiconductor layer is disposed on the first nitride semiconductor layer. The first transistor is disposed on the second nitride semiconductor layer. The first transistor includes a first control electrode, a first current electrode and a second current electrode. The clamping device is disposed on the second nitride semiconductor layer. The clamping device includes a second transistor and a third transistor. The second transistor includes a second control electrode, a third current electrode, and a fourth current electrode. The third transistor includes a third control electrode and a fifth current electrode. The third current electrode of the second transistor is coupled with the third control electrode of the third transistor. A first potential midpoint is connected to the fifth current electrode of the third transistor and the first current electrode of the first transistor. A second potential midpoint is connected to the fourth current electrode of the second transistor and the second current electrode of the first transistor. The present disclosure provides a semiconductor device structure including a clamping device. The clamping device may be coupled to a working device. The clamping device may include a first transistor and a second transistor electrically connected to the working device in parallel. When there is a short-circuit between a current electrode of the working device and ground, the potential difference between the switch electrode and the current electrode of the working device may be fixed. BRIEF DESCRIPTION OF THE DRAWINGS Aspects of the present disclosure are readily understood from the following detailed description when read with the accompanying figures. It should be noted that various features may not be drawn to scale. In fact, the dimensions of the various features may be arbitraril