US-12620803-B2 - Failsafe node voltage setting circuit

Abstract

Provided is a circuit that sets a voltage of a failsafe node. The circuit includes a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to a supply voltage of a supply voltage node. The circuit includes first and second control transistors configured to control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and a pad node voltage of a pad node corresponding to logical one and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero.

Inventors

• Manoj Kumar Tiwari
• Sandeep Kaushik
• Zia PARVEEN

Assignees

• STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date

20260505

Application Date

20240307

Claims (20)

1. 1 . A circuit, comprising: a failsafe node; a supply voltage node configured to provide a supply voltage; a pad node having a pad node voltage; a first voltage setting transistor configured to operate in a conductive state to set a voltage of the failsafe node to the supply voltage of the supply voltage node; first and second control transistors configured to: control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and the pad node voltage corresponding to logical one; and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero; a second voltage setting transistor configured to operate in the conductive state to set the voltage of the failsafe node to the pad node voltage in response to the supply voltage corresponding to the logical zero; and a third voltage setting transistor configured to operate in the conductive state to set the voltage of the failsafe node to the supply voltage in response to the pad node voltage corresponding to the logical zero.
2. 2 . The circuit of claim 1 , wherein the first voltage setting transistor has: a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to a control node.
3. 3 . The circuit of claim 2 , wherein the first control transistor has: a first conduction terminal and a control terminal coupled to the pad node, and a second conduction terminal coupled to the control node.
4. 4 . The circuit of claim 3 , wherein the second control transistor has: a first conduction terminal coupled to the pad node, a second conduction terminal coupled to the control node, and a control terminal coupled to the supply voltage node.
5. 5 . The circuit of claim 2 , comprising: a leakage stage configured to drain current from the control node.
6. 6 . The circuit of claim 1 , wherein: the second voltage setting transistor has: a first conduction terminal coupled to the pad node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to the supply voltage node, and the third voltage setting transistor has: a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to the pad node.
7. 7 . A method, comprising: controlling, by first and second control transistors, a first voltage setting transistor to operate in a conductive state in response to both a supply voltage of a supply voltage node and a pad node voltage of a pad node corresponding to logical one, wherein the second control transistor includes: a first conduction terminal coupled to the pad node; a second conduction terminal coupled to a control node; and a control terminal coupled to the supply voltage node; controlling, by the first and second control transistors, the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero; and in response to controlling the first voltage setting transistor to operate in the conductive state, setting, by the first voltage setting transistor, a voltage of a failsafe node to the supply voltage of the supply voltage node.
8. 8 . The method of claim 7 , wherein the first voltage setting transistor has: a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to the control node.
9. 9 . The method of claim 8 , wherein the first control transistor has: a first conduction terminal and a control terminal coupled to the pad node, and a second conduction terminal coupled to the control node.
10. 10 . The method of claim 8 , comprising: draining, by a leakage stage, current from the control node.
11. 11 . The method of claim 7 , comprising: operating, by a second voltage setting transistor, in the conductive state to set the voltage of the failsafe node to the pad node voltage in response to the supply voltage corresponding to the logical zero, and operating, by a third voltage setting transistor, in the conductive state to set the voltage of the failsafe node to the supply voltage in response to the pad node voltage corresponding to the logical zero.
12. 12 . The method of claim 11 , wherein: the second voltage setting transistor has: a first conduction terminal coupled to the pad node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to the supply voltage node, and, the third voltage setting transistor has: a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to the pad node.
13. 13 . A system, comprising: a buffer including a pad node and configured to: during non-failsafe operation, set a pad node voltage of the pad node based on an input signal; and during failsafe operation, set the pad node voltage based on a voltage of a failsafe node; and a circuit including: a first voltage setting transistor configured to operate in a conductive state to set the voltage of the failsafe node to a supply voltage of a supply voltage node; first and second control transistors configured to: control the first voltage setting transistor to operate in the conductive state in response to both the supply voltage and the pad node voltage corresponding to logical one; and control the first voltage setting transistor to operate in a nonconductive state in response to one of the supply voltage or the pad node voltage corresponding to the logical one and another one of the supply voltage or the pad node voltage corresponding to logical zero; a second voltage setting transistor configured to operate in the conductive state to set the voltage of the failsafe node to the pad node voltage in response to the supply voltage corresponding to the logical zero; and a third voltage setting transistor configured to operate in the conductive state to set the voltage of the failsafe node to the supply voltage in response to the pad node voltage corresponding to the logical zero.
14. 14 . The system of claim 13 , wherein the first voltage setting transistor has: a first conduction terminal coupled to the supply voltage node, a second conduction terminal coupled to the failsafe node, and a control terminal coupled to a control node.
15. 15 . The system of claim 14 , wherein the first control transistor has: a first conduction terminal and a control terminal coupled to the pad node; and a second conduction terminal coupled to the control node.
16. 16 . The system of claim 15 , wherein the second control transistor has: a first conduction terminal coupled to the pad node, a second conduction terminal coupled to the control node, and a control terminal coupled to the supply voltage node.
17. 17 . The system of claim 14 , wherein the circuit includes: a leakage stage configured to drain current from the control node.
18. 18 . The system of claim 17 , wherein the leakage stage includes a first conduction terminal coupled to the control node and a second conduction terminal coupled to a reference voltage node.
19. 19 . The system of claim 18 , wherein the leakage stage includes a diode-connected transistor.
20. 20 . The system of claim 13 , wherein: the second voltage setting transistor includes: a first conduction terminal coupled to the pad node; a second conduction terminal coupled to the failsafe node; and a control terminal coupled to the supply voltage node; and the third voltage setting transistor includes: a first conduction terminal coupled to the supply voltage node; a second conduction terminal coupled to the failsafe node; and a control terminal coupled to the pad node.

Description

BACKGROUND Technical Field The present disclosure is directed to a circuit that sets a voltage of a failsafe node and, in particular, a circuit that sets a voltage of a failsafe node of a buffer or a transmitter. Description of the Related Art In many circuits, including buffers, transmitters and input/output (I/O) drivers, normal operation conditions are predicated upon a supply voltage being provided at a particular supply voltage level. A reduction in the supply voltage, particularly to ground voltage or zero voltage, may result in operational failures of a circuit. Accordingly, the circuit may be controlled to default to a failsafe mode of operation. BRIEF SUMMARY Provided is a voltage setting circuit for a failsafe node. The voltage setting circuit sets the voltage of the failsafe node to the higher of a supply voltage and a pad node voltage of a pad node. The pad node may be a node over which the output signal of a device (such as a buffer, transmitter or driver, among others) is provided. The voltage of the failsafe node may be used to control the output of the device during a failsafe mode of operation. In the failsafe mode of operation, the supply voltage may correspond to a logical zero (for example, zero volts) instead of corresponding to a logical one (for example, 1.8 volts). Alternatively, the supply voltage may drop to a voltage level that is greater than zero volts but less than 1.8 volts. The pad node voltage may correspond to a normal supply voltage level (e.g., 1.8 volts) that was supplied before occurrence of the failsafe condition. The voltage setting circuit also controls the voltage of the failsafe node when both the supply voltage and the pad node voltage correspond to a logical one and the failsafe mode of operation is in effect. The voltage setting circuit sets the voltage of the failsafe node to the supply voltage. Accordingly, the voltage setting circuit aids in avoiding or mitigating leakage current in the device as compared to setting the voltage of the failsafe node to a voltage that is less than the supply voltage. BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS FIG. 1 shows a circuit diagram of a buffer. FIG. 2 shows a voltage setting circuit for a failsafe node of the buffer. DETAILED DESCRIPTION FIG. 1 shows a circuit diagram of a buffer 100. Although the buffer 100 is shown as a push-pull transmitter, it is noted that any other type of buffer may be used. The buffer 100 may be an input/output (I/O) driver. The buffer 100 has failsafe functionality as described herein. The buffer 100 includes a transmitting stage 102, first and second input switches 104, 106, first and second failsafe switches 108, 110 and first and second output transistors 112, 114. The transmitting stage 102 has an input over which the transmitting stage 102 receives an input signal and first and second outputs. The buffer 100 may be part of a bidirectional buffer. The first input switch 104 has a first conduction terminal coupled to the first output of the transmitting stage 102 and a second conduction terminal coupled to a first node 116. The second input switch 106 has a first conduction terminal coupled to the second output of the transmitting stage 102 and a second conduction terminal coupled to a second node 118. The first failsafe switch 108 has first conduction terminal coupled to a failsafe (FS) node 120 and a second conduction terminal coupled to the first node 116. The second failsafe switch 110 has a first conduction terminal coupled to the second node 118 and a second conduction terminal coupled to a reference voltage node 122. The reference voltage node 122 may be a ground node. The first output transistor 112 has a first conduction terminal coupled to a supply voltage node 124, a second conduction terminal coupled to a pad node 126, a control terminal coupled to the first node 116 and a body terminal coupled to the supply voltage node 124. The supply voltage node 124 may be configured to provide a supply voltage (VDDE). During normal operation, the supply voltage (VDDE) may correspond to logical one or be asserted, whereby, for example, the supply voltage (VDDE) may be 1.8 volts (V). The second output transistor 114 has a first conduction terminal coupled to the pad node 126, a second conduction terminal coupled to the reference voltage node 122, a control terminal coupled to the second node 118 and a body terminal coupled to the reference voltage node 122. During normal operation (non-failsafe mode operation), the first and second input switches 104, 106 are closed and the first and second failsafe switches 108, 110 are open. The transmitting stage 102 may be any type of logic configured to set the voltage of the first and second nodes 116, 118 based on the state of the input signal. When the input signal is asserted (e.g., logical one, activated or having a voltage level corresponding to the supply voltage (VDDE)), the transmitting stage 102 outputs a first signal, over its first