US-12620883-B2 - Fast flash analog-to-digital converter

US12620883B2US 12620883 B2US12620883 B2US 12620883B2US-12620883-B2

Abstract

A 2-bit fast flash analog-to-digital converter circuit and related methods designed for use with multi-level converters in particular to achieve: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages. One embodiment includes a voltage input configured to be coupled to a multi-level converter fly capacitor; a comparator coupled to the voltage input and a first reference voltage input and having a first binary output indicating whether the input voltage is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input and to second and third reference voltage inputs, the circuit configured to provide a second binary output indicating whether the input voltage is inside or outside a voltage window defined by respective voltages on the second reference and third reference voltage inputs.

Inventors

Gary Chunshien Wu

Assignees

MURATA MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230724

Claims (20)

1 . A voltage detector circuit including: a voltage input configured to be coupled to a voltage from a fly capacitor of a multi-level power converter; a first comparator having a first input coupled to the voltage input and a second input coupled to a first reference voltage, the first comparator having a first output indicating whether the voltage on the voltage input is higher or lower than a voltage on the first reference voltage; and a circuit coupled to the voltage input, a second reference voltage greater than the first reference voltage, and a third reference voltage less than the first reference voltage, the circuit configured to provide a second output of a first value when the voltage on the voltage input is inside a voltage window defined by the second reference voltage and the third reference voltage, and a second value when the voltage on the voltage input is greater than the second reference voltage, and the second value when the voltage on the voltage input is less than the third reference voltage.
2 . The voltage detector circuit of claim 1 , further including a controller coupled to a plurality of the voltage detector circuits corresponding to a plurality of fly capacitors, the controller configured to dynamically size the voltage window as a function of the voltages from the plurality of fly capacitors.
3 . The voltage detector circuit of claim 2 , wherein the controller is further configured to: balance charge across the plurality of fly capacitors in a priority order determined based on the second output.
4 . The voltage detector circuit of claim 1 , further including a controller coupled to a plurality of the voltage detector circuits corresponding to a plurality of fly capacitors, the controller configured to dynamically increase a size of the voltage window if the voltages from the plurality of fly capacitors are all outside a prior voltage window size, and to dynamically decrease the size of the voltage window if the voltages from the plurality of fly capacitors are all inside the prior voltage window size.
5 . The voltage detector circuit of claim 1 , wherein the voltage from the fly capacitor is scaled before being coupled to the voltage input.
6 . The voltage detector circuit of claim 1 , wherein an amount of voltage is subtracted from the voltage from the fly capacitor before being coupled to the voltage input.
7 . The voltage detector circuit of claim 6 , wherein the amount of subtracted voltage is a fixed value less than the voltage from the fly capacitor.
8 . The voltage detector circuit of claim 6 , wherein the amount of subtracted voltage is a percentage of a target voltage for the fly capacitor.
9 . The voltage detector circuit of claim 1 , wherein the circuit coupled to the voltage input, the second reference voltage, and the third reference voltage includes a second comparator coupled to the voltage input and the second reference voltage and a third comparator coupled to the voltage input and the third reference voltage, the outputs of the first and second comparators being coupled to a logic gate, wherein the first and second comparators and the logic gate provide the second output indicating whether the voltage on the voltage input is inside or outside a voltage window defined by respective voltages on the second reference voltage and the third reference voltage.
10 . The voltage detector circuit of claim 9 , wherein the voltage from the fly capacitor is scaled before being coupled to the voltage input.
11 . The voltage detector circuit of claim 9 , wherein an amount of voltage is subtracted from the voltage from the fly capacitor before being coupled to the voltage input.
12 . The voltage detector circuit of claim 11 , wherein the amount of subtracted voltage is a fixed value less than the voltage from the fly capacitor.
13 . The voltage detector circuit of claim 11 , wherein the amount of subtracted voltage is a percentage of a target voltage for the fly capacitor.
14 . The voltage detector circuit of claim 9 , wherein the second reference voltage is greater than the first reference voltage, and the third reference voltage is less than the first reference voltage.
15 . A multi-level power converter including: a multi-level converter cell configured to receive an input voltage V IN from a voltage source and transform the input voltage V IN into an output voltage V OUT , the multi-level converter cell including a set of power switches coupled in series and a set of fly capacitors coupled in series with certain respective power switches and in parallel with power switches in between the certain respective power switches; and for each fly capacitor in the set of fly capacitors, a voltage detector circuit including: a voltage input coupled to an associated fly capacitor of the multi-level converter cell, the voltage input configured to receive a voltage from the associated fly capacitor, a comparator having a first input coupled to the voltage input and a second input coupled to a first reference voltage input, the comparator having a first binary output indicating whether the voltage on the voltage input is higher or lower than a voltage on the first reference voltage input, and a circuit coupled to the voltage input, a second reference voltage input with a greater voltage than the first reference voltage input, and a third reference voltage input with a lower voltage than the first reference voltage input, the circuit configured to provide a second binary output indicating a first value when the voltage on the voltage input is inside a voltage window defined by the respective voltages on the second reference voltage input and the third reference voltage input, and a second value when the voltage on the voltage input is greater than the second reference voltage input, and the second value when the voltage on the voltage input is less than the third reference voltage input.
16 . The multi-level power converter of claim 15 , wherein the voltage from the fly capacitor is scaled before being coupled to the voltage input.
17 . The multi-level power converter of claim 15 , wherein an amount of voltage is subtracted from the voltage from the fly capacitor before being coupled to the voltage input.
18 . The multi-level power converter of claim 17 , wherein the amount of subtracted voltage is a fixed value less than the voltage from the fly capacitor.
19 . The multi-level power converter of claim 17 , wherein the amount of subtracted voltage is a percentage of a target voltage for the fly capacitor.
20 . The multi-level power converter of claim 15 , further including a resistive divider configured to be coupled to a reference voltage source and configured to provide: the first reference voltage at a first node coupled to the first reference voltage input; the second reference voltage at a second node coupled to the second reference voltage input; and the third reference voltage at a third node coupled to the third reference voltage input.

Description

BACKGROUND (1) Technical Field This invention relates to electronic circuits, and more particularly to fast flash analog-to-digital converters. (2) Background Many electronic products, particularly mobile computing and/or communication products and components (e.g., notebook computers, ultra-book computers, tablet devices, LCD and LED displays) require multiple voltage levels. For example, radio frequency (RF) transmitter power amplifiers may require relatively high voltages (e.g., 12V or more), whereas logic circuitry may require a low voltage level (e.g., 1-3V). Still other circuitry may require an intermediate voltage level (e.g., 5-10V). Direct current power converters are often used to generate a lower or higher voltage from a common power source, such as a battery, solar cells, and rectified AC sources. Power converters which generate a lower output voltage level from a higher input voltage power source are commonly known as buck converters, so-called because the output voltage VOUT is less than the input voltage VIN, and hence the converter is “bucking” the input voltage. Power converters which generate a higher output voltage level from a lower input voltage power source are commonly known as boost converters, because VOUT is greater than VIN. Some power converters may be either a buck converter or a boost converter depending on which terminals are used for input and output. Some power converters may provide an inverted output. One type of direct current power converter known as a multi-level power converter includes charge transfer capacitors as energy storage elements coupled by controlled power switches so as to transfer charge from VIN to VOUT. Such charge transfer capacitors are commonly known as “fly capacitors” or “pump capacitors”. Every time a fly capacitor is used (i.e., not bypassed), the electrical energy flowing through that fly capacitor generally will either charge it or discharge it. This creates a control problem: what configurations and in what order can the fly capacitors be switched while maintaining their average voltage? This is the charge-balance problem that multi-level converter circuits introduce—balancing charge on the fly capacitors in order to maintain their average voltage. Proper multi-level power converter operation requires fly capacitor voltages to be continuously balanced to corresponding target voltages. Determining a suitable charge-balance method can become exceedingly difficult as the complexity of a multi-level converter circuit increases. Most conventional control methods rely on establishing a sequence of linked state-changes to try to achieve charge balance. Control systems based on long sequences of power switch states generally assume that all system variables—such as input voltage and output current—are constant during the sequence. This is unrealistic for a real-world environment, where all system variables tend to be dynamic. In particular, the voltage across each fly capacitor is a dynamic variable, the value of which is a useful—and often necessary—factor in determining charge-balance across the fly capacitors of a multi-level converter circuit. Accordingly, there is a need for circuits and methods for more effectively and efficiently determining the voltage across each fly capacitor of a multi-level converter circuit. The present invention addresses this and other needs, and has applicability beyond multi-level converter circuits. SUMMARY The present invention encompasses a 2-bit fast flash analog-to-digital converter (ADC) circuit and related methods. The 2-bit fast flash ADC has been designed for use with multi-level converters in particular to achieve all the following: high conversion speed, high resolution, small layout area, low power, and the ability to meet the requirements for properly balancing fly capacitor voltages in a multi-level converter cell. However, the inventive 2-bit fast flash ADC may be used in other applications where such characteristics are desirable. One embodiment of a fast flash analog-to-digital converter circuit in accordance with the present invention includes a voltage input configured to be coupled to a voltage from a fly capacitor of a multi-level power converter; a comparator having a first input coupled to the voltage input and a second input coupled to a first reference voltage input, the second comparator having a first binary output indicating whether the voltage on the voltage input is higher or lower than a voltage on the first reference voltage input; and a circuit coupled to the voltage input, a second reference voltage input, and a third reference voltage input, the circuit configured to provide a second binary output indicating whether the voltage on the voltage input is inside or outside a voltage window defined by respective voltages on the second reference voltage input and the third reference voltage input. One method of converting an analog voltage from a fly capacitor of a multi-level power convert