Search

US-12620889-B2 - BOOT UVLO detection scheme for high voltage applications

US12620889B2US 12620889 B2US12620889 B2US 12620889B2US-12620889-B2

Abstract

A buck converter including a high-side switch, a low-side switch and a bootstrap (BOOT), under-voltage lockout (UVLO) circuit. The BOOT UVLO circuit includes a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event. The BOOT UVLO circuit further includes a logic gate configured to receive the UVLO_Z and a high-side ON, (HSON) signal, the HSON signal is for controlling a switching of the high-side switch. The logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby immediately switch OFF the high-side switch when the HSON signal is ON.

Inventors

  • Jairo Olivares
  • Alejandro Vera
  • Mitchell Levine

Assignees

  • NEXPERIA B.V
  • Nexperia Technology (Shanghai) Ltd.

Dates

Publication Date
20260505
Application Date
20240328

Claims (17)

  1. 1 . A buck converter comprising: a high-side switch; a low-side switch; and a bootstrap (BOOT) under-voltage lockout (UVLO) circuit, wherein the BOOT UVLO circuit comprises: a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event, wherein the BOOT UVLO detection element is configured to output an UVLO signal (UVLO_Z), in case of the BOOT UVLO event; and a logic gate configured to receive the UVLO_Z and a high-side ON (HSON), signal; wherein the HSON signal is for controlling a switching of the high-side switch; and wherein the logic gate is configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby switch OFF the high-side switch when the HSON signal is ON.
  2. 2 . The buck converter according to claim 1 , further comprising: a gate driver circuit, wherein the logic gate has an output that is an input to the gate driver circuit, and wherein the gate driver circuit has an output that is an input to a gate of the high-side switch.
  3. 3 . The buck converter according to claim 1 , wherein the high-side switch has a source that is connected to the BOOT UVLO circuit via the SW.
  4. 4 . The buck converter according to claim 1 , wherein the high-side switch has a gate that is connected to an input of a high-side (HS) gate-source voltage (V GS ) detection element configured to detect whether the high-side switch is turned ON or OFF based on the V GS ; and wherein the V GS detection element is configured to output a high-side OK (HSOK) signal indicative of the high-side switch being turned ON or OFF.
  5. 5 . The buck converter according to claim 2 , wherein the high-side switch has a source that is connected to the BOOT UVLO circuit via the SW.
  6. 6 . The buck converter according to claim 4 , further comprising a logic element, wherein the logic element is configured to: detect, based on the HSOK signal, that the high-side switch is turned OFF while the HSON signal is ON; and start a BOOT refresh algorithm when it is detected that the high-side switch is turned OFF while the HSON signal is ON.
  7. 7 . The buck converter according to claim 6 , wherein the BOOT refresh algorithm is configured to sequentially: switch ON the low-side switch using a low-side ON (LSON) signal; try to switch ON the high-side switch using the HSON signal; and determine, based on the HSOK signal, whether the high-side switch is turned ON.
  8. 8 . The buck converter according to claim 7 , wherein the BOOT refresh algorithm is configured to repeat the sequential steps until it is determined, based on the HSOK signal, that the high-side switch is turned ON.
  9. 9 . The buck converter according to claim 7 , wherein the BOOT refresh algorithm is configured to: apply a first time delay after switching ON the low-side switch using the LSON signal; and apply a second time delay after trying to switch ON the high-side switch using the HSON signal.
  10. 10 . The buck converter according to claim 8 , wherein the BOOT refresh algorithm is configured to: apply a first time delay after switching ON the low-side switch using the LSON signal; and apply a second time delay after trying to switch ON the high-side switch using the HSON signal.
  11. 11 . The buck converter according to claim 10 , wherein the first time delay is about 300 ns and the second time delay is about 100 ns.
  12. 12 . A method of detecting a bootstrap (BOOT), under-voltage lockout (UVLO), event in a buck converter, the method comprising the steps of: detecting, based on a high-side OK (HSOK) signal indicative of a high-side switch of the buck converter being turned ON or OFF, that the high-side switch is turned OFF while a high-side ON (HSON) signal for controlling the switching of the high-side switch is ON; and starting a BOOT refresh algorithm when it is detected that the high-side switch is turned OFF while the HSON signal is ON.
  13. 13 . The method according to claim 12 , wherein the BOOT refresh algorithm comprises sequentially: switching ON a low-side switch of the buck converter using a low-side ON (LSON) signal; trying to switch ON the high-side switch using the HSON signal; and determining, based on the HSOK signal, whether the high-side switch is turned ON.
  14. 14 . The method according to claim 13 , wherein the BOOT refresh algorithm further comprises repeating the sequential steps until it is determined, based on the HSOK signal, that the high-side switch is turned ON.
  15. 15 . The method according to claim 13 , wherein the BOOT refresh algorithm further comprises: applying a first time delay after switching ON the low-side switch using the LSON signal; and applying a second time delay after trying to switch ON the high-side switch using the HSON signal.
  16. 16 . The method according to claim 14 , wherein the BOOT refresh algorithm further comprises: applying a first time delay after switching ON the low-side switch using the LSON signal; and applying a second time delay after trying to switch ON the high-side switch using the HSON signal.
  17. 17 . The method according to claim 15 , wherein the first time delay is about 300 ns and the second time delay is about 100 ns.

Description

BACKGROUND 1. Field of the Disclosure The present disclosure relates to buck converters. More specifically, the present disclosure relates to a bootstrap (BOOT) under-voltage lockout (UVLO) detection in a buck converter. 2. Description of the Related Art A buck converter, also known as a step-down converter, is a type of direct current (DC) to DC converter circuit used to efficiently step down a higher input voltage to a lower output voltage. It is widely used in various applications such as power supplies, battery chargers and voltage regulators. The basic operation of a buck converter involves the controlled switching of a power transistor to regulate the output voltage. In a power converter circuit, such as a buck converter, the bootstrap (BOOT) domain pertains to the voltage supply used to drive the high-side switching element, often a metal-oxide-semiconductor field-effect transistor (MOSFET) or an insulated gate bipolar transistor (IGBT). The high-side switch is responsible for controlling the flow of current from the input to the output in these converters. The bootstrap circuit of the buck converter typically includes a bootstrap capacitor. The bootstrap capacitor provides a floating voltage supply to the high-side MOSFET driver to switch the input voltage to the load. During the OFF state of the high-side MOSFET the bootstrap capacitor charges up to value of the boot refresh rail. This is typically on the order of the max gate-source voltage (VGS) that the high side FET can tolerate. This charging is usually accomplished through a diode connected between the input voltage and the bootstrap capacitor. When the high-side MOSFET is turned ON, the voltage across its gate and source needs to be higher than the input voltage to ensure proper conduction. The charge stored in the bootstrap capacitor provides this higher voltage, allowing the high-side MOSFET to switch effectively. The bootstrap capacitor must be large enough to supply the required gate charge during the entire ON time of the high-side MOSFET, ensuring continuous operation of the buck converter. SUMMARY A summary of aspects of certain examples disclosed herein is set forth below. It should be understood that these aspects are presented merely to provide the reader with a brief summary of these certain embodiments and that these aspects are not intended to limit the scope of this disclosure. Indeed, this disclosure may encompass a variety of aspects and/or a combination of aspects that may not be set forth. The present disclosure presents an under-voltage lockout (UVLO) detection scheme and a scheme for bootstrap capacitor charging during UVLO for a BOOT domain of a buck converter. The solution of the present disclosure is particularly useful in high voltage applications. Advantageously, the solution of the present disclosure does not require any extra level shifters or other additional high voltage devices to detect and deal with UVLO events. According to an aspect of the present disclosure, a buck converter is presented. The buck converter includes a high-side switch and a low-side switch. The buck converter may further include a BOOT UVLO circuit. The BOOT UVLO circuit may include a BOOT UVLO detection element configured to compare a BOOT voltage with a switch node (SW) voltage to determine an occurrence of a BOOT UVLO event. The BOOT UVLO detection element may be configured to output an UVLO signal (UVLO_Z) in case of the BOOT UVLO event. The BOOT UVLO circuit may further include a logic gate configured to receive the UVLO_Z and a high-side ON (HSON) signal, wherein the HSON signal is for controlling a switching of the high-side switch. The logic gate may be configured to negate the HSON signal when receiving the UVLO_Z while the HSON signal is ON, to thereby switch OFF the high-side switch when the HSON signal is ON. In an embodiment, the buck converter may further include a gate driver circuit. An output of the logic gate may be input to the gate driver circuit. An output of the gate driver circuit may input to a gate of the high-side switch. In an embodiment, a source of the high-side switch may be connected to the BOOT UVLO circuit via the SW. In an embodiment, a gate of the high-side switch may be connected to an input of a high-side (HS) gate-source voltage (VGS) detection element configured to detect whether the high-side switch is turned ON or OFF based on the VGS. The VGS detection element may be configured to output a high-side OK (HSOK) signal indicative of the high-side switch being turned ON or OFF. In an embodiment, the buck converter may further include a logic element. The logic element may be configured to detect, based on the HSOK signal, that the high-side switch is turned OFF while the HSON signal is ON. The logic element may further be configured to start a BOOT refresh algorithm when it is detected that the high-side switch is turned OFF while the HSON signal is ON. In an embodiment, the BOOT refresh algorithm may b