US-12620894-B2 - Maximum frequency adjustment control for a switched capacitor power converter

Abstract

A device comprises a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC), and a second comparator to generate a first control signal based on the first voltage and a threshold voltage. A sensor is to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal. A frequency divider circuit is to generate a second clock signal based on the first control signal and the second control signal, and in some embodiments, further based on one of the first clock signal or a third clock signal. Controller circuitry is to operate switch circuitry of the SCPC based on the first clock signal.

Inventors

• Keng Chen
• Huanhuan Zhang
• Arvind Raghavan
• Tamir Salus
• Christopher SCHAEF
• Gayathri Devi Sridharan

Assignees

• INTEL CORPORATION

Dates

Publication Date

20260505

Application Date

20221109

Claims (20)

1. 1 . A device comprising: a first comparator to generate a first clock signal based on a reference voltage and a first voltage at an output of a switched-capacitor power converter (SCPC); a second comparator to generate a first control signal based on the first voltage and a threshold voltage; a sensor, coupled to the first comparator, to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal; a frequency divider circuit coupled to receive the first control signal and the second control signal, the frequency divider circuit to generate a second clock signal based on the first control signal and the second control signal; and controller circuitry coupled to the first comparator and the frequency divider circuit, the controller circuitry to operate switch circuitry of the SCPC based on the first clock signal; wherein the frequency divider circuit is to generate the second clock signal further based on a third clock signal, and the first comparator is to generate the first clock signal further based on the second clock signal.
2. 2 . The device of claim 1 , wherein the sensor is to generate the second control signal based on the level of the current of the first clock signal, and the sensor comprises: a pulse counter to generate a pulse count signal based on the first clock signal; and wherein the controller circuitry is further to determine the level of current based on a number of occurrences of the pulse count signal within a particular period of time.
3. 3 . The device of claim 1 , wherein the sensor is to generate the second control signal based on the duty cycle of the first clock signal, and the sensor comprises: timing circuitry to provide an off-time voltage indicative of a length of an off time of the duty cycle of the first clock signal; and a third comparator to receive the off-time voltage and to generate an off-time signal when the off time of the duty cycle of the first clock signal exceeds a threshold time.
4. 4 . The device of claim 3 , wherein the timing circuitry comprises a capacitor, at least one current source to charge the capacitor, and a plurality of first switches to selectively couple the capacitor with the at least one current source.
5. 5 . The device of claim 1 , wherein the threshold voltage is one of a first threshold voltage or a second threshold voltage.
6. 6 . The device of claim 1 , wherein the second control signal is to select one of two or more divide-by circuitries of the frequency divider circuit to be applied to the third clock signal.
7. 7 . The device of claim 1 , wherein the first control signal is to select a bypass circuitry of the frequency divider circuit.
8. 8 . A device comprising: a first comparator to generate a first clock signal based on a reference voltage, and on a first voltage at an output of a switched-capacitor power converter (SCPC); a second comparator to generate a first control signal based on the first voltage and a threshold voltage; a sensor, coupled to the first comparator, to generate a second control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal; a frequency divider circuit coupled to receive the first control signal and the second control signal, the frequency divider circuit to generate a second clock signal based on the first control signal and the second control signal; and controller circuitry coupled to the first comparator and the frequency divider circuit, the controller circuitry to operate switch circuitry of the SCPC based on the first clock signal; wherein the frequency divider circuit is to generate the second clock signal further based on the first clock signal, and wherein the first comparator is to generate the first clock signal further based on a third clock signal.
9. 9 . The device of claim 8 , wherein the sensor is to generate the second control signal based on the level of the current of the first clock signal, and the sensor comprises: a pulse counter to generate a pulse count signal based on the first clock signal; and wherein the controller circuitry is further to determine the level of current based on a number of occurrences of the pulse count signal within a particular period of time.
10. 10 . The device of claim 8 , wherein the sensor is to generate the second control signal based on the duty cycle of the first clock signal, and the sensor comprises: timing circuitry to provide an off-time voltage indicative of a length of an off time of the duty cycle of the first clock signal; and a third comparator to receive the off-time voltage and to generate an off-time signal when the off time of the duty cycle of the first clock signal exceeds a threshold time.
11. 11 . The device of claim 10 , wherein the timing circuitry comprises a capacitor, at least one current source to charge the capacitor, and a plurality of first switches to selectively couple the capacitor with the at least one current source.
12. 12 . The device of claim 8 , wherein the threshold voltage is one of a first threshold voltage or a second threshold voltage.
13. 13 . The device of claim 8 , wherein the second control signal is to select one of two or more divide-by circuitries of the frequency divider circuit to be applied to the first clock signal; and the first control signal is to select a bypass circuitry of the frequency divider circuit.
14. 14 . The device of claim 8 , wherein the sensor is further to generate a third control signal based on one of a level of a current of the first clock signal, or a duty cycle of the first clock signal; and further comprising an interleaving unit coupled to receive the first control signal from the second comparator, the third control signal from the sensor, the second clock signal from the frequency divider circuit, and the third clock signal, wherein the interleaving unit is to generate a fourth clock signal based on the second clock signal, and wherein the controller circuitry coupled to receive the fourth clock signal.
15. 15 . A device comprising: a first comparator to generate a first clock signal based on a reference voltage, and on a first voltage at an output of a switched-capacitor power converter (SCPC); a second comparator to generate a first control signal based on the first voltage and a threshold voltage; a sensor, coupled to the first comparator, to generate a second control signal based on the one of a level of a current of the first clock signal, or a duty cycle of the first clock signal; a frequency divider circuit coupled to receive the first control signal and the second control signal, the frequency divider circuit to generate a second clock signal based on the first control signal and the second control signal; and controller circuitry coupled to the first comparator and the frequency divider circuit, the controller circuitry to operate switch circuitry of the SCPC based on the first clock signal; wherein the frequency divider circuit is to generate the second clock signal further based on one of the first clock signal or a third clock signal, and wherein the first comparator is to generate the first clock signal further based on one of the second clock signal or the third clock signal.
16. 16 . The device of claim 15 , wherein the sensor is to generate the second control signal based on the level of the current of the first clock signal, and the sensor comprises: a pulse counter to generate a pulse count signal based on the first clock signal; and wherein the controller circuitry is further to determine the level of current based on a number of occurrences of the pulse count signal within a particular period of time.
17. 17 . The device of claim 15 , wherein the sensor is to generate the second control signal based on the duty cycle of the first clock signal, and the sensor comprises: timing circuitry to provide an off-time voltage indicative of a length of an off time of the duty cycle of the first clock signal; and a third comparator to receive the off-time voltage and to generate an off-time signal when the off time of the duty cycle of the first clock signal exceeds a threshold time.
18. 18 . The device of claim 17 , wherein the timing circuitry comprises a capacitor, at least one current source to charge the capacitor, and a plurality of first switches to selectively couple the capacitor with the at least one current source.
19. 19 . The device of claim 15 , wherein the threshold voltage is one of a first threshold voltage or a second threshold voltage.
20. 20 . The device of claim 15 , wherein the second control signal is to select one of two or more divide-by circuitries of the frequency divider circuit to be selectively applied to the first clock signal or the third clock signal; and the first control signal is to select a bypass circuitry of the frequency divider circuit.

Description

BACKGROUND 1. Technical Field This disclosure generally relates to power converter circuitry and more particularly, but not exclusively, to adjusting the maximum frequency used to control a frequency-controlled switched-capacitor power converter. 2. Background Art A switched-capacitor power converter (SCPC) is one type of voltage regulator technology which provides space and cost efficiencies due to its primary reliance on using only capacitors and switch circuitry. As a result of the switching process, the output voltage of an SCPC can have a periodic variation or “ripple.” Keeping ripple low and providing high conversion efficiency in SCPCs is important. BRIEF DESCRIPTION OF THE DRAWINGS The various embodiments of the present invention are illustrated by way of example, and not by way of limitation, in the figures of the accompanying drawings and in which: FIG. 1 shows a functional block diagram illustrating features of a system to provide a regulated voltage in which a frequency of a clock signal used to provide the voltage is adjusted based on a load condition according to an embodiment. FIG. 2 shows a functional block diagram illustrating features of a system to provide a regulated voltage in which a frequency of a clock signal used to provide the voltage is adjusted based on a load condition according to an embodiment. FIG. 3 shows a functional block diagram illustrating features of a signal generator for adjusting a frequency of a clock signal based on a load condition in which the load condition is detected based on a clock signal output by a feedback comparator using a pulse counting mechanism according to some embodiments. FIG. 4 shows a timing diagram illustrating features of operations by the signal generator of FIG. 3 according to an embodiment. FIG. 5 shows a functional block diagram illustrating features of a signal generator for adjusting a frequency of a clock signal based on a load condition in which the load condition is detected based on a clock signal output by a feedback comparator using a duty cycle detection mechanism according to some embodiments. FIG. 6 shows a timing diagram illustrating features of operations by the signal generator of FIG. 5 according to an embodiment. FIG. 7A and FIG. 7B show functional block diagrams illustrating features of signal generators of that adjust a frequency of a clock signal used by a feedback comparator based on a detected load condition according to various embodiments. FIG. 8 shows a functional block diagram illustrating features of a signal generator that adjusts the frequency of a clock signal output from a feedback comparator based on a detected load condition according to various embodiments. FIG. 9 shows a circuit block diagram illustrating features of a computer device to adjust a frequency of a clock signal used by a feedback comparator, or to adjust the frequency of a clock signal output from a feedback comparator, based on a detected load condition according to an embodiment. DETAILED DESCRIPTION FIG. 1 shows features of a system 100 to provide a regulated voltage according to various embodiments. System 100 illustrates one example of an embodiment wherein a regulated voltage is provided to a load with a switched-capacitor power converter circuit, wherein a load condition is detected and a maximum frequency used by a signal generator is adjusted based on the detected load condition. As shown in FIG. 1, system 100 comprises a switched-capacitor power converter (SCPC) 104 that provides an output voltage Vout 112 to a “load” 102 via a trace or copper pour 103. The system 100 may include an output capacitor Cout 105, for example, to reduce ripple in Vout 112. SCPC 104 is separated from load 102 by a distance D corresponding with a length of trace 103 between SCPC 104 and the target load 102. In some implementations, the distance D may be of sufficient length that performance is affected. For example, in a system-on-a-chip (SoC), the distance D from SCPC 104 to one or more components of a load 102 may be such that parasitic inductance IP of the trace 103 is relatively large. This relatively large inductance, together with the capacitance of output capacitor Cout (or other capacitance), can cause relatively large voltage ringing at node N proximate or near to load 102. SCPC 104 may monitors load conditions, e.g., Vout 112, at node N, or at any other suitable point along trace 103. Ringing of Vout 112 at a monitoring point may be not be a serious problem under heavy load conditions, i.e., when the amount of current supplied by SCPC 104 is relatively large. However, during light load conditions, large voltage ringing may cause large output voltage ripple and may significantly reduce the efficiency of SCPC 104. An advantage of various embodiments is that SCPC 104 monitors load conditions and adjusts the maximum switching frequency of a clock signal input to a feedback comparator, which reduces output voltage ripple and improves efficiency under