US-12620895-B2 - Balance system to regulate the voltage of the fly capacitor of a three-level buck acting on ramps

US12620895B2US 12620895 B2US12620895 B2US 12620895B2US-12620895-B2

Abstract

A three-level DC-DC converter includes a power-stage with high and low-side transistors, a flying capacitor, and an inductor coupled between an output tap of the power-stage and an output node of the converter. A feedback-divider is coupled in parallel with an output capacitor between the output node and ground and generates a feedback-voltage. A ramp-generator generates a first ramp-signal based on a constant reference-voltage and generates a second ramp-signal based on a difference between a voltage across the flying capacitor and one-half the input-voltage. Control-circuitry generates an error-signal based on a comparison between the feedback-voltage and a reference, generates a first high-side control-signal and a first low-side control-signal for the power-stage, based on a comparison between the first ramp-signal and the error-signal, and generates a second high-side control-signal and a second low-side control-signal for the power-stage, based on a comparison between the second ramp-signal and the error-signal.

Inventors

Marco LA PILA
Giuseppe Platania
Placido Salvatore BATTIATO

Assignees

STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date: 20260505
Application Date: 20240122

Claims (16)

1 . A DC-DC converter, comprising: a power stage comprising: a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; a flying capacitor coupled between the high-side tap and the low-side tap; an inductor coupled between the output tap and an output node; an output capacitor coupled between the output node and ground; and a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider; a ramp generator configured to generate a first ramp signal and a second ramp signal, wherein the ramp generator generates the first ramp signal as a function of a constant reference voltage and generates the second ramp signal as a function of a difference between a voltage across the flying capacitor and one half the input voltage; control circuitry configured to: generate an error signal based on a comparison between the feedback voltage and a reference voltage; generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on a comparison between the second ramp signal and the error signal.
2 . The DC-DC converter of claim 1 , wherein the ramp generator comprises: first ramp generation circuitry comprising: a first voltage-to-current converter configured to generate a first charging current based upon the constant reference voltage; a first timing capacitor configured to be charged by the first charging current; and a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
3 . The DC-DC converter of claim 2 , wherein the first voltage-to-current converter comprises: a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output; a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain; a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal.
4 . The DC-DC converter of claim 2 , wherein the ramp generator further comprises: second ramp generation circuitry comprising: a second voltage-to-current converter configured to generate a second charging current based upon the difference between the voltage across the flying capacitor and one half the input voltage; a second timing capacitor configured to be charged by the second charging current; and a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.
5 . The DC-DC converter of claim 4 , wherein the second voltage-to-current converter comprises: a second amplifier having a non-inverting input receiving a delta voltage whose slope is proportional to the difference between one half the input voltage and the voltage across the flying capacitor, an inverting input coupled to ground through a second sense resistor, and an output; a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output of the second amplifier, and a drain; a third p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, assertion of the second reset signal corresponding to the second edge of the clock signal.
6 . The DC-DC converter of claim 4 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a first input coupled to receive one half the input voltage, a second input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the second input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.
7 . The DC-DC converter of claim 4 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a non-inverting input coupled to receive one half the input voltage, an inverting input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the inverting input through a balance capacitor, wherein a delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.
8 . A method of operating a DC-DC converter, the method comprising: converting an input voltage to an output voltage using a power stage; generating a first ramp signal as a function of a constant reference voltage; generating a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage; generating an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage; generating a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and generating a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.
9 . The method of claim 8 , wherein generating the first ramp signal comprises: generating a first charging current based upon the constant reference voltage; receiving the first charging current to charge a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
10 . The method of claim 9 , wherein generating the second ramp signal comprises: generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor; receiving the second charging current to charge a second timing capacitor; discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.
11 . A DC-DC converter, including: a power stage configured to convert an input voltage to an output voltage; a ramp generator configured to: generate a first ramp signal as a function of a constant reference voltage; and generate a second ramp signal as a function of a difference between one half the input voltage and a voltage across a flying capacitor of the power stage; an error amplifier configured to generate an error signal based on a comparison between a reference voltage and a feedback voltage representative of the output voltage; and control circuitry configured to: generate a first high-side control signal for a first high-side transistor of the power stage, and a first low-side control signal for a first low-side transistor of the power stage, based on a comparison between the first ramp signal and the error signal; and generate a second high-side control signal for a second high-side transistor of the power stage, and a second low-side control signal for a second low-side transistor of the power stage, based on a comparison between the second ramp signal and the error signal.
12 . The DC-DC converter of claim 11 , wherein the ramp generator generates the first ramp signal by: generating a first charging current based upon the constant reference voltage; receiving the first charging current to charge a first timing capacitor; and discharging the first timing capacitor at a first edge of a clock signal; and wherein the first ramp signal is generated as a function of the charging and discharging of the first timing capacitor.
13 . The DC-DC converter of claim 12 , wherein the ramp generator generates the second ramp signal by: generating a second charging current based on a delta voltage whose slope is proportional to a difference between one half the input voltage and the voltage across the flying capacitor; receiving the second charging current to charge a second timing capacitor; and discharging the second timing capacitor at a second edge of the clock signal; wherein the second ramp signal is generated as a function of the charging and discharging of the second timing capacitor.
14 . A DC-DC converter, comprising: a power stage comprising: a first high-side transistor coupled between an input voltage and a high-side tap, a second high-side transistor coupled between the high-side tap and an output tap, a first low-side transistor coupled between a low-side tap and ground, and a second low-side transistor coupled between the output tap and the low-side tap; a flying capacitor coupled between the high-side tap and the low-side tap; an inductor coupled between the output tap and an output node; an output capacitor coupled between the output node and ground; and a feedback divider coupled in parallel with the output capacitor, with a feedback voltage being formed at a tap of the feedback divider; a ramp generator comprising: first ramp generation circuitry comprising: a first voltage-to-current converter configured to generate a first charging current based upon a constant reference voltage; a first timing capacitor configured to be charged by the first charging current; and a first reset transistor configured to discharge the first timing capacitor at a first edge of a clock signal; wherein a first ramp signal is generated as a function of the charging and discharging of the first timing capacitor; and wherein the first voltage-to-current converter comprises: a first amplifier having a non-inverting input receiving the constant reference voltage, an inverting input coupled to ground through a first sense resistor, and an output; a first n-channel transistor having a source coupled to ground through the first sense resistor, a gate coupled to the output of the first amplifier, and a drain; a first p-channel transistor having a source coupled to a supply voltage, a drain coupled to the drain of the first n-channel transistor, and a gate coupled to the drain of the first p-channel transistor; a second p-channel transistor having a source coupled to the supply voltage, a drain coupled to the first timing capacitor, and a gate coupled to the gate of the first p-channel transistor; and a second n-channel transistor having a drain coupled to the first timing capacitor, a source coupled to ground, and a gate coupled to a first reset signal, assertion of the first reset signal corresponding to the first edge of the clock signal; second ramp generation circuitry comprising: a second voltage-to-current converter configured to generate a second charging current based upon a difference between a voltage across the flying capacitor and one half the input voltage; a second timing capacitor configured to be charged by the second charging current; and a second reset transistor configured to discharge the second timing capacitor at a second edge of the clock signal; wherein a second ramp signal is generated as a function of the charging and discharging of the second timing capacitor; wherein the second voltage-to-current converter comprises: a second amplifier having a non-inverting input receiving a delta voltage whose slope is proportional to the difference between one half the input voltage and the voltage across the flying capacitor, an inverting input coupled to ground through a second sense resistor, and an output; a third n-channel transistor having a source coupled to ground through the second sense resistor, a gate coupled to the output of the second amplifier, and a drain; a third p-channel transistor having a source coupled to the supply voltage, a drain coupled to the drain of the third n-channel transistor, and a gate coupled to the drain of the third p-channel transistor; a fourth p-channel transistor having a source coupled to the supply voltage, a drain coupled to the second timing capacitor, and a gate coupled to the gate of the third p-channel transistor; and a fourth n-channel transistor having a drain coupled to the second timing capacitor, a source coupled to ground, and a gate coupled to a second reset signal, assertion of the second reset signal corresponding to the second edge of the clock signal; control circuitry configured to: generate an error signal based on the feedback voltage and a reference voltage; generate a first high-side control signal for the first high-side transistor, and a first low-side control signal for the first low-side transistor, based on the first ramp signal and the error signal; and generate a second high-side control signal for the second high-side transistor, and a second low-side control signal for the second low-side transistor, based on the second ramp signal and the error signal.
15 . The DC-DC converter of claim 14 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a first input coupled to receive one half the input voltage, a second input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the second input through a balance capacitor, wherein the delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.
16 . The DC-DC converter of claim 14 , further comprising balancing circuitry, the balancing circuitry comprising an amplifier having a non-inverting input coupled to receive one half the input voltage, an inverting input coupled to the voltage across the flying capacitor through a balance resistor, and an output coupled to the inverting input through a balance capacitor, wherein the delta voltage is generated at the output of the amplifier, the delta voltage having a slope that is proportional to the difference between one half the input voltage and the voltage across the flying capacitor; and wherein the second voltage-to-current converter generates the second charging current based upon the delta voltage.

Description

TECHNICAL FIELD This disclosure is directed to the field of power electronics and, in particular, to control systems for three-level buck converters. BACKGROUND DC-DC converters are frequently utilized in modern electronic devices, providing the necessary voltage transformation for a variety of applications. Buck converters, in particular, are utilized for their efficiency in stepping down voltage. Two-level buck converters are widely utilized in low to medium power applications. However, as power requirements increase, issues such as electromagnetic interference, switching losses, and the need for larger inductors and capacitors become more significant. To address these concerns, three-level buck converters have been developed and utilize additional switches and capacitors to create intermediate voltage levels. This design reduces the voltage stress on each switch, allowing for the use of lower-rated and more efficient components. A known three-level buck converter 10 is now described with reference to FIG. 1. The three-level buck converter 10 includes: a first n-channel transistor MN1 having its drain connected to an input voltage VIN and its source connected to a first tap TAP1, a second n-channel transistor MN2 having its drain connected to the first tap TAP1 and its source connected to a second tap TAP2, a third n-channel transistor MN3 having its drain connected to the second tap TAP2 and its source connected to a third tap TAP3, and a fourth n-channel transistor MN4 having its drain connected to the third tap TAP3 and its source coupled to ground. The gates of n-channel transistors MN1, MN2, MN3, MN4 are driven by respective control voltages HS1, HS2, LS2, LS1 generated by a logic/driver circuit 15—assertion of control voltage HS1 turns on transistor MN1 while deassertion of HS1 control voltage turns off transistor MN1, assertion of control voltage HS2 turns on transistor MN2 while deassertion of control voltage HS2 turns off transistor MN2, assertion of control voltage LS2 turns on transistor MN3 while deassertion of control voltage LS2 turns off transistor MN3, and assertion of control voltage LS1 turns on transistor MN4 while deassertion of control voltage LS1 turns off transistor MN4. A flying capacitor CFLY is connected between first tap TAP1 and third tap TAP3. An inductor L is connected between the second tap TAP2 and an output capacitor COUT at which an output voltage VOUT is produced. A feedback divider is formed by feedback resistors RFB1, RFB2 connected in series between the output capacitor COUT and ground, with a feedback voltage VFB being formed at the tap between resistors RFB1, RFB2. A proportional-integral-derivative (PID) controller 14 receives the feedback voltage VFB and a reference voltage VREF as input and generates an error voltage VERROR based upon the difference between the feedback voltage VFB and the reference voltage VREF. A first comparator 11 receives the error voltage VERROR at its non-inverting input, compares it to a first ramp signal RAMP1 received at its inverting input from a ramp generator 13, and provides output OUT1 to the logic/driver circuit 15. A second comparator 12 receives the error voltage VERROR at its non-inverting input, compares it to a second ramp signal RAMP2 received at its inverting input from the ramp generator 13, and provides output OUT2 to the logic/driver circuit 15. The ramp signals RAMP1 and RAMP2 are 180° out of phase. Operation with a duty cycle of less than 50%, where VOUT<VIN/2, includes three phases. In the first phase, control voltages HS1 and LS2 are asserted, resulting in current flow from VIN, through transistor MN1, through capacitor CFLY, and out to inductor L through transistor MN3. As shown in the graphs of FIGS. 2A-2B, during this first phase, assuming VCFLY=VIN/2, the voltage VLX formed at the second tap TAP2 is equal to one half the input voltage, namely VLX=VIN/2, and the inductor current increases with a rate of change of VIN/2-VOUTL. In the second phase, control voltages LS1 and LS2 are asserted to turn on transistors MN3 and MN4, resulting in in discharge of the inductor L. As shown in the graphs of FIGS. 2A-2B, during this second phase, the voltage VLX is equal to 0 and the inductor current decreases with a rate of change of −VOUT/L. In the third phase, control voltages HS2 and LS1 are asserted to turn on transistors MN2 and MN4, resulting in discharge of the flying capacitor CFLY to inductor L. As shown in the graphs of FIGS. 2A-2B, during this third phase, the voltage VLX formed at second tap TAP2 is equal to one half the input voltage, namely VLX=VIN/2, and the inductor current increases with a rate of change of VIN/2-VOUTL. As shown in FIG. 2C, the order of phase execution is Phase 1, Phase 2, Phase 3, Phase 2, Phase 1, Phase 2, Phase 3, Phase 2, etc. Operation with a duty cycle of greater than 50%, where VOUT>VIN/2, includes the above described first and third phases, as well as a fourth phase. In the fourth phase,