US-12620896-B2 - High efficiency power conversion circuit having high voltage tolerance

US12620896B2US 12620896 B2US12620896 B2US 12620896B2US-12620896-B2

Abstract

A power conversion circuit converting power between a bus voltage at a bus node and a first voltage at a first node includes: a bus switch coupled between the bus node and a second node which has a second voltage; plural conversion switches coupled, with at least one conversion capacitor, to the first node and the second node. In a power conversion mode, the plural conversion switches convert a power between the second voltage and the first voltage via a switched capacitor power conversion method, and plural sub-clamp circuits respectively clamping a drain-gate voltage of respective switch of a group of switches to not exceed a drain-gate clamp voltage, so that when the bus node is applied with a bus maximum rating voltage, respective drain-source voltages of the bus switch and the respective switch in the respective corresponding plural conversion switches are smaller than a corresponding breakdown voltage.

Inventors

Tsung-Wei Huang
Ye-Sing Luo
Sheng-Kai Fan

Assignees

RICHTEK TECHNOLOGY CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230615
Priority Date: 20230418

Claims (14)

1 . A power conversion circuit, which is configured to operably perform power conversion between a bus voltage at a bus node and a first voltage at a first node; the power conversion circuit comprising: a bus switch, which is coupled between the bus node and a second node, wherein the second node has a second voltage; a plurality of conversion switches coupled, with at least one conversion capacitor, to the first node and the second node, wherein in a power conversion mode, the bus switch is turned ON, and the plurality of the conversion switches are configured to operably switch the at least one conversion capacitor periodically, thereby power conversion between the second voltage and the first voltage via a switched capacitor power conversion method is performed; and a clamp circuit which includes a plurality of sub-clamp circuits, wherein each of the plurality of sub-clamp circuits is configured to operably clamp respective drain-gate voltages of respective corresponding switches of a group of switches, so that the respective drain-gate voltages of the respective corresponding switches of the group of switches do not exceed a respective drain-gate clamp voltage, wherein the group of switches include the bus switch and at least one of the plurality of the conversion switches, so that when the bus node is applied with a bus maximum rating voltage, respective drain-source voltages of the bus switch and respective corresponding plurality of conversion switches are smaller than respective breakdown voltages; wherein the bus maximum rating voltage is higher than the respective breakdown voltages of the bus switch and the respective corresponding plurality of conversion switches.
2 . The power conversion circuit as claimed in claim 1 , wherein the group of switches are sequentially coupled in series.
3 . The power conversion circuit as claimed in claim 1 , wherein the respective breakdown voltages of the bus switch and the respective corresponding plurality of conversion switches are of a same level, wherein the group of switches include k switches, wherein k is a quotient of the bus maximum rating voltage divided by a drain-source clamp voltage and k is a positive integer, wherein the drain-source clamp voltage is defined as: respective drain-source voltages of respective corresponding switches of the group of switches in a situation where the respective drain-gate voltages of the respective corresponding switches of the group of switches are clamped at the respective drain-gate clamp voltage.
4 . The power conversion circuit as claimed in claim 1 , wherein the respective breakdown voltage is smaller than ½ of the bus maximum rating voltage.
5 . The power conversion circuit as claimed in claim 1 , wherein when one switch of the group of switches is clamped at the respective drain-gate clamp voltage by the clamp circuit, a drain-gate voltage of the one switch of the group of switches is clamped at a sum of the respective drain-gate clamp voltage and an ON threshold voltage of the one switch of the group of switches, such that the drain-gate voltage of the one switch of the group of switches is smaller than the respective breakdown voltage.
6 . The power conversion circuit as claimed in claim 1 , wherein at least one of the plurality of the sub-clamp circuits includes: at least one diode or at least one diode-connected transistor having its gate and drain being electrically connected to each other, wherein the respective drain-gate clamp voltage is correlated with a forward voltage of the at least one diode, a reverse breakdown voltage of the at least one diode or an ON threshold voltage of the at least one diode-connected transistor.
7 . The power conversion circuit as claimed in claim 6 , wherein, when the at least one of the plurality of the sub-clamp circuits includes the at least one diode, the at least one diode includes: a Zener diode having a reverse terminal coupled to a positive clamp terminal; and a reverse blocking diode having a forward terminal coupled to a forward terminal of the Zener diode and having a reverse terminal coupled to a negative clamp terminal; wherein the positive clamp terminal and the negative clamp terminal are coupled to a drain and a gate, respectively, of one switch of the group of switches, so as to clamp a drain-gate voltage of the one switch of the group of switches; wherein the reverse blocking diode is configured to operably cut off a current which occurs in a case where a voltage at the negative clamp terminal is higher than a voltage at the positive clamp terminal; wherein the respective drain-gate clamp voltage is correlated with a sum of a forward voltage of the reverse blocking diode and a reverse breakdown voltage of the Zener diode.
8 . The power conversion circuit as claimed in claim 1 , further comprising: a comparator, which is configured to operably compare the bus voltage with an over voltage threshold to generate a bias voltage switching signal; and a bias voltage switching circuit, which is configured to operably switch a body bias voltage of the bus switch according to the bias voltage switching signal, wherein when the bus voltage is higher than the over voltage threshold, the bias voltage switching circuit is configured to operably switch the body bias voltage to the bus voltage or else switch the body bias voltage to the second voltage.
9 . The power conversion circuit as claimed in claim 8 , wherein the plurality of the sub-clamp circuits include: a first bus sub-clamp circuit and a second bus sub-clamp circuit; wherein the first bus sub-clamp circuit is configured to operably clamp a voltage between the bus node and a gate of the bus switch, so as to clamp a voltage difference between the bus node and the second node to be smaller than a breakdown voltage of the bus switch; wherein the second bus sub-clamp circuit is configured to operably clamp a voltage between the second node and the gate of the bus switch, so as to clamp the voltage difference between the second node and the bus node to be smaller than the breakdown voltage of the bus switch.
10 . The power conversion circuit as claimed in claim 8 , wherein the over voltage threshold is smaller than the bus maximum rating voltage.
11 . The power conversion circuit as claimed in claim 1 , wherein the plurality of the conversion switches include: a first high side switch, a second high side switch, a first low side switch and a second low side switch, four of which are connected in series between the second node and a ground node; wherein the at least one conversion capacitor includes a first conversion capacitor; wherein in the power conversion mode, the plurality of the conversion switches are configured to operably control a first end of the first conversion capacitor to periodically switch between the first node and the second node and control a second end of the first conversion capacitor to periodically switch between the first node and the ground node, such that in a steady state, a voltage across the first conversion capacitor is ½ of the second voltage and the first voltage is ½ of the second voltage.
12 . The power conversion circuit as claimed in claim 11 , wherein the at least one of the plurality of the conversion switches in the group of switches include one of following: the first high side switch; the first high side switch and the second high side switch; or the first high side switch, the second high side switch and the first low side switch.
13 . The power conversion circuit as claimed in claim 11 , wherein the power conversion circuit is further configured to operably switch an inductor, wherein the inductor is coupled between the first node and a switching node, wherein a portion of the plurality of the conversion switches are coupled to the switching node; wherein in a steady state, a voltage across the at least one conversion capacitor is 1/P-fold of the second voltage, wherein P is a real number greater than one; wherein the plurality of the conversion switches are configured to operably switch the at least one conversion capacitor and the inductor periodically, so as to perform power conversion between the first voltage and the second voltage in an at least three-level pulse width modulation (PWM) scheme.
14 . The power conversion circuit as claimed in claim 1 , wherein in the power conversion mode, the respective drain-gate clamp voltage is greater than a maximum of the respective drain-gate voltages of the respective corresponding switches of the group of switches during periodical switching for power conversion.

Description

CROSS REFERENCE The present invention claims priority to U.S. 63/386,162 filed on Dec. 5, 2022 and claims priority to TW 112114455 filed on Apr. 18, 2023. BACKGROUND OF THE INVENTION Field of Invention The present invention relates to a power conversion circuit; particularly, it relates to such power conversion circuit having high voltage tolerance and such power conversion circuit capable of maintaining high efficiency. Description of Related Art Please refer to FIG. 1A and FIG. 1B. FIG. 1A shows a schematic diagram of a conventional power conversion circuit, whereas, FIG. 1B shows a schematic diagram of another conventional power conversion circuit. Each of the conventional power conversion circuit 910 of FIG. 1A and the conventional power conversion circuit 920 of FIG. 1B includes: plural conversion switches M0˜M4. Each of the conventional power conversion circuit 910 of FIG. 1A and the conventional power conversion circuit 920 of FIG. 1B is configured to perform power conversion between a voltage VBS and a voltage VO. The plural conversion switches M0˜M4 are configured to periodically switch a capacitor C1, thereby performing power conversion between a voltage V1 and the voltage VO via a switched capacitor power conversion method, wherein the switch M0 functions as a path switch. In a common practical application, because an absolute maximum ratings (AMR) of the voltage VBS can undesirably reach for example 22 volts (V), the prior arts adopt lateral diffused MOS (LDMOS) transistor capable of withstanding high voltage to overcome this major drawback. In the conventional power conversion circuit 910 shown in FIG. 1A, the switch M1 is designed as a LDMOS transistor. In a sleep mode, the switches M0˜M4 are all OFF. Because a body diode of the switch M0 has a configuration of being forward-coupled (i.e., a current input terminal is coupled to the voltage VBS), the switch M1 will unwantedly suffer a high voltage resulted from the voltage VBS. As a consequence, in this case, it is required for the switch M1 to be designed as the LDMOS transistor having a breakdown voltage up to 24V, such that the switch M1 will be able to withstand the AMR of the voltage VBS equal to 22V. In the conventional power conversion circuit 920 shown in FIG. 1B, the switch M0 is designed as a LDMOS transistor. In a sleep mode, the switches M0˜M4 are all OFF. Because a body diode of the switch M0 has a configuration of being reverse-coupled (i.e., the current output terminal is coupled to the voltage VBS), the switch M0 will unwantedly suffer the high voltage resulted from the voltage VBS. As a consequence, in this case, it is required for the switch M0 to be designed as the LDMOS transistor having a breakdown voltage equal to 24V, such that the switch M0 will be able to withstand the AMR of the voltage VBS up to 22V. The prior art power conversion circuit 910 shown in FIG. 1A and the prior art power conversion circuit 920 shown in FIG. 1B have the following drawbacks: although the prior arts shown in FIG. 1A and FIG. 1B can withstand the AMR through adopting a LDMOS transistor, nevertheless, because a high voltage device (e.g., a LDMOS transistor) usually has a relatively greater ON resistance, ON power loss will be undesirably increased, thus unwantedly reducing charging efficiency. From another perspective, with a predetermined target ON resistance, the manufacturing cost will be undesirably increased. SUMMARY OF THE INVENTION From one perspective, the present invention provides a power conversion circuit, which is configured to operably perform power conversion between a bus voltage at a bus node and a first voltage at a first node; the power conversion circuit comprising: a bus switch, which is coupled between the bus node and a second node, wherein the second node has a second voltage; a plurality of conversion switches coupled, with at least one conversion capacitor, to the first node and the second node, wherein in a power conversion mode, the bus switch is turned ON, and t the plurality of the conversion switches are configured to operably switch the at least one conversion capacitor and periodically, thereby power conversion between the second voltage and the first voltage via a switched capacitor power conversion method is performed; and a clamp circuit which includes a plurality of sub-clamp circuits, wherein the respective plurality of sub-clamp circuits are configured to operably clamp respective drain-gate voltages of respective corresponding switches of a group of switches, so that respective drain-gate voltages of the respective corresponding switches of the group of switches do not exceed respective corresponding drain-gate clamp voltages, wherein the group of switches include the bus switch and at least one of the plurality of the conversion switches, so that when the bus node is applied with a bus maximum rating voltage, respective drain-source voltages of the bus switch and the respective corresponding plurality of