US-12620901-B2 - Deeply integrated voltage regulator architectures

Abstract

A system is disclosed. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip.

Inventors

• David Lidsky

Assignees

• Empower Semiconductor, Inc.

Dates

Publication Date

20260505

Application Date

20230921

Claims (18)

1. 1 . A system comprising: a substrate; a first semiconductor die disposed on the substrate and including a load circuit, wherein the first semiconductor die further includes an error signal generation circuit; a second semiconductor die disposed on the substrate and including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit internal within the second semiconductor die; and wherein the control circuit is arranged to control a power delivered to the load circuit via directly controlling the plurality of power switches; and wherein the control circuit receives an error signal from the error signal generation circuit and in response controls a power delivered to the load circuit via the plurality of power switches.
2. 2 . The system of claim 1 , wherein the control circuit is arranged to control the power delivered to the load circuit in response to receiving an error signal from the error signal generation circuit.
3. 3 . The system of claim 2 , wherein the power converter circuit is coupled to the load circuit at a node and wherein the error signal represents a difference between a regulated voltage at the node and a reference voltage.
4. 4 . The system of claim 2 , wherein the error signal is an analog voltage.
5. 5 . The system of claim 2 , wherein the error signal is a digital signal.
6. 6 . The system of claim 2 , wherein the error signal generation circuit comprises an analog-to-digital converter configured to generate the error signal.
7. 7 . The system of claim 2 , wherein the power converter circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first semiconductor die.
8. 8 . The system of claim 2 , wherein the power converter circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second semiconductor die.
9. 9 . The system of claim 2 , wherein the plurality of power switches are integrated on the second semiconductor die.
10. 10 . The system of claim 3 , further comprising a reference voltage generator configured to generate the reference voltage, and wherein the reference voltage generator is integrated on the first semiconductor die.
11. 11 . The system of claim 2 , wherein the power converter circuit comprises: a capacitor connected to the load circuit; one or more inductors connected to the load circuit; and wherein the plurality of power switches, the capacitor, and the one or more inductors collectively form a voltage regulator.
12. 12 . The system of claim 11 , wherein the voltage regulator is multiphase.
13. 13 . A method of forming a system, the method comprising: attaching a first semiconductor die to a substrate, the first semiconductor die including a load circuit, wherein the first semiconductor die further includes an error signal generation circuit; attaching a second semiconductor die to the substrate, the second semiconductor die including a power converter circuit arranged to deliver power to the load circuit, the power converter circuit including a plurality of power switches coupled to a control circuit internal within the second semiconductor die; and wherein the control circuit is arranged to control a power delivered to the load circuit via directly controlling the plurality of power switches.
14. 14 . The method of claim 13 , wherein the control circuit is arranged to control the power delivered to the load circuit in response to receiving an error signal from the error signal generation circuit.
15. 15 . The method of claim 14 , wherein the power converter circuit is coupled to the load circuit at a node and wherein the error signal represents a difference between a regulated voltage at the node and a reference voltage.
16. 16 . The method of claim 14 , wherein the error signal generation circuit comprises an analog-to-digital converter configured to generate the error signal.
17. 17 . The method of claim 14 , wherein the power converter circuit comprises a capacitor connected to the load circuit, wherein the capacitor is integrated on the first semiconductor die.
18. 18 . The method of claim 14 , wherein the power converter circuit comprises one or more inductors connected to the load circuit, wherein the inductors are formed on the substrate separate from the first and second semiconductor die.

Description

CROSS-REFERENCES TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 18/163,820, filed Feb. 2, 2023, entitled DEEPLY INTEGRATED VOLTAGE REGULATOR ARCHITECTURES, which is a continuation of U.S. patent application Ser. No. 17/811,042, filed Jul. 6, 2022, entitled DEEPLY INTEGRATED VOLTAGE REGULATOR ARCHITECTURES, which is a continuation of U.S. patent application Ser. No. 17/208,851, filed Mar. 22, 2021, entitled DEEPLY INTEGRATED VOLTAGE REGULATOR ARCHITECTURES, which is a continuation of U.S. patent application Ser. No. 16/727,909, filed Dec. 26, 2019, entitled DEEPLY INTEGRATED VOLTAGE REGULATOR ARCHITECTURES, which claims the benefit of U.S. Provisional Application No. 62/785,143, filed Dec. 26, 2018, entitled INTEGRATED VOLTAGE REGULATOR, the disclosures of all of which are incorporated herein by reference in their entirety. FIELD OF THE INVENTION The present application generally pertains to power delivery circuits, and more particularly to circuits which deliver power to a load using multiple phases. BACKGROUND OF THE INVENTION New circuits have increased power needs. Therefore, power delivery systems having improved control schemes are needed. BRIEF SUMMARY OF THE INVENTION One inventive aspect is a system. The system includes a substrate, and a first chip on the substrate, where a load circuit is integrated on the first chip. The system also includes a second chip on the substrate, where a power delivery circuit is configured to deliver current to the load circuit according to a regulated voltage at a node. The power delivery circuit includes a first circuit configured to generate an error signal based at least in part on the regulated voltage, and a voltage generator including power switches configured to modify the regulated voltage according to the error signal, where the first circuit of the power delivery circuit is integrated on the first chip, and where at least a portion of the power switches of the power delivery circuit are integrated on the second chip. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 depicts an illustrative simplified schematic of a system. FIG. 2 is a cross-sectional schematic view of a IC package. FIG. 3 depicts an illustrative simplified schematic of a power delivery control circuit that can be used in a variety of electronic systems. FIG. 4 is a waveform diagram illustrating wave forms for signals of the power delivery control circuit 100 illustrated in FIG. 1. FIG. 5 is a waveform diagram illustrating wave forms for signals of the power delivery control circuit 100 illustrated in FIG. 1. FIG. 6 is a diagram illustrating Tc (time between starts of phase pulses) and Verr (error voltage) dependence on load current. FIG. 7A is a schematic illustration of a power delivery engine. FIG. 7B illustrates one example of the waveforms for the power delivery engine 500 illustrated in FIG. 7A. FIG. 8 is a schematic illustration of a power delivery engine. FIG. 9 is a schematic illustration of a control timer circuit. FIG. 10 is a schematic illustration of a comparator mode control circuit. FIGS. 11 and 12 illustrate an embodiment of a voltage to time circuit. FIGS. 13 and 14 illustrate an embodiment of a voltage to time circuit. FIGS. 15 and 16 illustrate an embodiment of inductor shorting. FIG. 17 is a schematic illustration of a control timer circuit. FIGS. 18-20 are schematic illustrations of compensation networks according to some embodiments. FIG. 21 is a flowchart of a repetitive switching sequence providing a continuous current output for the switched regulation circuit in FIG. 5 according to an embodiment of the invention. FIG. 22 is a timing diagram of voltages and currents within the switched regulation circuit of FIG. 7A according to the switching sequence in FIG. 21. FIG. 23 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21. FIG. 24 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21. FIG. 25 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21. FIG. 26 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21. FIG. 27 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21; FIG. 28 is a schematic of the switched regulation circuit shown in FIG. 7A in a particular switch configuration according to the switching sequence in FIG. 21. DETAILED DESCRIPTION OF THE INVENTION Particular embodiments of the invention are illustrated herein in conjunction with the drawings. FIG. 1 depicts an illustrative simplified schematic of system 10 including a power delivery cir