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US-12620909-B2 - Power conversion system for reducing dc-link capacitor stress

US12620909B2US 12620909 B2US12620909 B2US 12620909B2US-12620909-B2

Abstract

A power conversion system includes a first direct current to alternating current (DC-AC) inverter, a second DC-AC inverter, an inverter controller, a direct current (DC)-link circuit connecting the first DC-AC inverter and the second DC-AC inverter, a neutral-point balancer (NPB), an NPB circuit, and an NPB controller. The inverter controller is configured to provide a pulse-width modulation (PWM), signal to the first DC-AC inverter and the second DC-AC inverter. The NPB circuit is configured to reduce low frequency current oscillations in the DC-link circuit by switching between a first state for transferring charge from a positive voltage line to a neutral voltage line, and a second state for transferring charge from the neutral voltage line to a negative voltage line. The NPB controller is configured to control the switching of the NPB circuit and is synchronized with the PWM signal from the inverter controller.

Inventors

  • Sebastian Rosado
  • Zhaohui Wang
  • Miroljub Bakic
  • Piniwan Thiwanka Bandara Wijekoon

Assignees

  • HUAWEI TECHNOLOGIES CO., LTD.

Dates

Publication Date
20260505
Application Date
20240419

Claims (20)

  1. 1 . A power conversion system comprising: a first direct current (DC)-alternating current (AC) inverter; a second DC-AC inverter; an inverter controller coupled to the first DC-AC inverter and the second first DC-AC inverter and configured to provide a pulse-width modulation, (PWM) signal to the first DC-AC inverter and the second DC-AC inverter; a DC-link circuit coupling the first DC-AC inverter and the second DC-AC inverter in parallel, the DC link circuit and comprising: a positive voltage line; a negative voltage line; a neutral voltage line; a high-frequency positive-line capacitor; a low-frequency positive-line capacitor, wherein each of the high-frequency positive-line capacitor and the low-frequency positive-line capacitor couples the neutral voltage line with the positive voltage line; a high-frequency negative-line capacitor; and a low-frequency negative-line capacitor, wherein each high-frequency negative-line capacitor and the low-frequency positive-line capacitor couples the neutral voltage line with the negative voltage line; a neutral-point balancer (NPB) circuit coupled to the DC-link circuit and configured to reduce low-frequency current oscillations in the DC-link circuit by switching between a first state for transferring charge from the positive voltage line to the neutral voltage line, and a second state for transferring charge from the neutral voltage line to the negative voltage line; and an NPB controller coupled to the NPB circuit, synchronized with the PWM signal, and configured to control the switching of the NPB circuit.
  2. 2 . The power conversion system of claim 1 , wherein the NPB circuit is a bidirectional DC-DC converter.
  3. 3 . The power conversion system of claim 2 , wherein the NPB circuit comprises: a first antiparallel diode; a positive line switch coupling the neutral voltage line with the positive voltage line using the first antiparallel diode; a second antiparallel diode; a negative line switch coupling the neutral voltage line with the negative voltage line using the second antiparallel diode; and one or more inductors coupled to a coupling point between the first antiparallel diode and the second antiparallel diode, and to the neutral voltage line.
  4. 4 . The power conversion system of claim 1 , wherein each of the first DC-AC inverter and the second DC-AC inverter is a three-level inverter.
  5. 5 . The power conversion system of claim 1 , wherein the inverter controller is further configured to set an inverter switching frequency, and wherein the NPB controller is further configured to set an NPB circuit switching frequency of the NPB circuit to an integer multiple of the inverter switching frequency.
  6. 6 . The power conversion system of claim 1 , wherein the NPB controller is further configured to: determine an optimal value for a phase angle between a carrier signal of the NPB circuit and the PWM signal at which high-frequency current oscillations in the DC-link circuit are below a threshold amplitude; and adjust a phase of the carrier signal to make the phase angle approach the optimal value.
  7. 7 . The power conversion system of claim 6 , wherein the NPB controller is further configured to determine the optimal value from a look-up table based on a ratio between a switching frequency of the NPB circuit and an inverter switching frequency of the inverter controller, and further based on a modulation used by the inverter controller.
  8. 8 . The power conversion system of claim 6 , wherein the NPB controller is further configured to determine the optimal value by monitoring a root mean square (RMS) value of a high-frequency current through the high-frequency positive-line capacitor and the high-frequency negative-line capacitor and adjusting the phase to set a value of the phase angle at which the RMS value is below the threshold amplitude.
  9. 9 . The power conversion system of claim 1 , wherein the inverter controller is further configured to set an inverter switching frequency, and wherein the high-frequency positive-line capacitor and the high-frequency negative-line capacitor are tuned to have a resonant frequency at a high-frequency that is a predefined frequency distance away from the inverter switching frequency.
  10. 10 . The power conversion system of claim 1 , wherein the high-frequency positive-line capacitor and the high-frequency negative-line capacitor are film type capacitors.
  11. 11 . The power conversion system of claim 1 , wherein the low-frequency positive-line capacitor and the low-frequency negative-line capacitor are configured to be tuned to make a branch coupling the low-frequency positive-line capacitor and the low-frequency negative-line capacitor have a resonant frequency in a frequency range between three times an output line frequency of the first DC-AC inverter and the second DC-AC inverter and a switching frequency of the first DC-AC inverter and the second DC-AC inverter.
  12. 12 . The power conversion system of claim 11 , wherein the resonant frequency is a predefined frequency distance away from boundaries of the frequency range.
  13. 13 . The power conversion system of claim 1 , wherein the low-frequency positive-line capacitor and the low-frequency negative-line capacitor are electrolytic type capacitors.
  14. 14 . The power conversion system of claim 2 , wherein each of the first DC-AC inverter and the second DC-AC inverter is a three-level inverter.
  15. 15 . The power conversion system of claim 2 , wherein the inverter controller is further configured to set an inverter switching frequency, and wherein the NPB controller is further configured to set a switching frequency of the NPB circuit to an integer multiple of the inverter switching frequency.
  16. 16 . The power conversion system of claim 2 , wherein the NPB controller is further configured to: determine an optimal value for a phase angle between a carrier signal of the NPB circuit and the PWM signal at which high-frequency current oscillations in the DC-link circuit are below a threshold amplitude; and adjust a phase of the carrier signal to make the phase angle approach the optimal value.
  17. 17 . The power conversion system of claim 2 , wherein the inverter controller is further configured to set an inverter switching frequency, and wherein the high-frequency positive-line capacitor and the high-frequency negative-line capacitor are configured to have a resonant frequency that is a predefined frequency distance away from the inverter switching frequency.
  18. 18 . The power conversion system of claim 2 , wherein the high-frequency positive-line capacitor and the high-frequency negative-line capacitor are film type capacitors.
  19. 19 . The power conversion system of claim 2 , wherein the low-frequency positive-line capacitor and the low-frequency negative-line capacitor are configured to make a branch coupling the low-frequency positive-line capacitor and the low-frequency negative-line capacitor have a resonant frequency in a frequency range between three times an output line frequency of the first DC-AC inverter and the second DC-AC inverter and a switching frequency of the first DC-AC inverter and the second DC-AC inverter.
  20. 20 . The power conversion system of claim 2 , wherein the low-frequency positive-line capacitor and the low-frequency negative-line capacitor are electrolytic type capacitors.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This is a continuation of International Patent Application No. PCT/EP2021/079157, filed on Oct. 21, 2021, the disclosure of which is hereby incorporated by reference in its entirety. TECHNICAL FIELD The disclosure relates generally to a power conversion system, and more particularly, the disclosure relates to the power conversion system for reducing DC-link capacitor stress in parallel connected multilevel power converters with higher operation efficiency and increased power density. BACKGROUND An inverter is an electronic device that turns direct current (DC) to alternating current (AC). The inverter is also configured to control speed and torque for electric motors, and also can be used for other DC/AC converter applications like photovoltaics power converters for solar inverters. Normally, the photovoltaic power converter includes three-phase DC/AC inverters based on two and multi-level circuit topologies with DC-link capacitors arranged in a split DC-bus. The DC-link capacitors optimize the capacitor usage with a voltage source and energy source by providing a low impedance path for circulation of high-frequency current components, thereby providing stability and grid code compliance in the power conversion system. The capacitors with low internal impedance and large root mean square (RMS) current capability, like film-type capacitors, on a DC/AC power converter 104A for a photovoltaic application 102, are shown in FIG. 1A. When it is necessary to reach higher power levels, it is necessary to connect two or more inverters in parallel with just hard paralleling or in interleaved mode. The capacitors providing a large capacitance in a small volume, like electrolytic-type capacitors, on two or more DC/AC power converters 104B-C for the photovoltaic application 102, is shown in FIG. 1B. In the AC side, the two or more DC/AC power converters 104B-C are connected to three-phase systems through AC inductors. One or more interleaving inductors are shown in FIG. 1C. The combination of capacitors with low internal impedance is shown in FIG. 1A and the capacitors providing the large capacitance as shown in FIG. 1B, allows an overall compact DC-link capacitor bank, that enables the solar inverter for high power density. The combination may be a circuit or connection of the parallel inverters, that relates to a shift between pulse width modulation (PWM) signals to trigger semiconductors in the circuit. The shift in the PWM is an angle shift in carrier waveforms that produce the PWM signals. An interleaving angle may be adjustable and an optimal value is related to an operation scheme of the interleaved inverters, thereby including a major effect in the optimal interleaving angle in the type of modulation. The use of interleaving in parallel converters has a significant impact on an RMS current circulating through the capacitors in the DC-link of the DC/AC inverters (i.e. the one or more DC/AC power converters 104B-C). The current value dependence is due to current cancellation effects at certain values of the interleaving angle. The value of the RMS current in the interleaving case is smaller than the algebraic sum of the RMS currents in the DC/AC inverters, with separate DC links. The interleaving may reduce the current stress on the DC link. But the current reduction affects the high-frequency components circulating through the capacitors. Also, the split DC link with two different capacitors with a predominantly different current component spectrum, as shown in FIG. 1A, the current reduction that interleaving can provide only impacts the high-frequency section. The low-frequency current components do not experience any benefit from the interleaving and are not be affected by the interleaving angle. The type of modulation used by the interleaved inverters has a major impact on the DC-link capacitor currents, as there are many types and variants of modulation schemes in use, each has its own characteristics in terms of operation performance, like power loss, current distortion, and stress on active circuit components as well as passive circuit components. Discontinuous PWM (DPWM) is widely used for the reduction of the power semiconductor switching losses. But in the multi-level inverters, DPWM produces an oscillation of the partial DC-link voltages. The oscillation is a characteristic of the modulation type employed on the multi-level inverters. Modulation waveforms may be in a modulation pattern that is based on the selection of the characteristics. For example, DPWM3 produces a smaller neutral voltage oscillation than DPWM1, but in terms of semiconductor power loss or AC line current distortion, the DPWM3 performance is lower than the DPWM1. The partial DC-link voltage oscillations are related to larger current stress on the capacitors, especially in the split DC-link, the voltage oscillations relate to low-frequency current stresses. A software-based approach and a hardwa