US-12620922-B2 - Method for operating a drive system, and drive system for carrying out a method

Abstract

In a method for operating a drive system and a drive system for carrying out a method, the electric motor is connected to the AC-side connection of an inverter, the DC-side connection of the inverter is connected to the DC-side connection of the rectifier via an inductance, a capacitance is connected to the DC-side connection of the inverter, a series circuit formed from a resistor and a braking chopper is connected to the DC-side connection of the inverter, and the braking chopper is operated with a pulse width modulation frequency, which is determined by a pseudo-random number generator.

Inventors

• Marcel Stark

Assignees

• SEW-EURODRIVE GMBH & CO. KG

Dates

Publication Date

20260505

Application Date

20220627

Priority Date

20210721

Claims (20)

1. 1 . A method of operating a drive system having a rectifier and at least one inverter with an electric motor, the electric motor connected to an AC-side connection of the inverter, a DC-side connection of the inverter connected to a DC-side connection of the rectifier via an inductance, a capacitance connected to the DC-side connection of the inverter and/or to the DC-side connection of the rectifier, a respective series circuit respectively formed from a resistor and a controllable semiconductor switch is connected to the DC-side connection of the inverter and/or to the DC-side connection of the rectifier, comprising: operating the series circuit, in a time period in which the series circuit is operated, with a pulse width modulation frequency is spaced apart from a resonant frequency of an oscillating circuit that includes the inductance and the capacitance; and generating the pulse width modulation frequency by a pseudo-random number generator.
2. 2 . The method according to claim 1 , wherein the inductance includes a line inductance, the capacitance includes a non-polar capacitor and/or a film capacitor, the series circuit arranged as a braking chopper, the oscillating circuit arranged as a resonant circuit, the generating including generating the pulse width modulation frequency by the pseudo-random number generator for a respective time duration.
3. 3 . The method according to claim 1 , wherein the pulse width modulation frequency is spaced apart from harmonic oscillations and/or harmonics of the resonant frequency of the oscillating circuit.
4. 4 . The method according to claim 1 , wherein a pulse width modulation period duration is determined by counting down of a counter loaded with a start value at a beginning of the pulse width modulation period, carried out in time with a first clock signal, and the start value is determined by the pseudo-random number generator.
5. 5 . The method according to claim 4 , wherein the pseudo-random number generator operates in time with a second clock signal.
6. 6 . The method according to claim 1 , wherein the pseudo-random number generator has a shift register fed back via a logic element.
7. 7 . The method according to claim 6 , wherein the logic element feeds a non-vanishing start value to the shift register upon switch-on, and thereafter, a result of a logical link of output signals of the shift register is fed to an input of the shift register.
8. 8 . The method according to claim 1 , wherein the pseudo-random number generator includes flip-flops, connected in series, having clock inputs synchronously supplied with a same clock signal and outputs fed to a counter as a start value, and outputs of the flip-flops are fed to a logic element having an output fed to the input of a first of the flip-flops connected in series.
9. 9 . The method according to claim 7 , wherein the logical link includes an EXOR link.
10. 10 . The method according to claim 5 , wherein the first clock signal is asynchronous with the second clock signal.
11. 11 . The method according to claim 10 , wherein the first clock signal is generated using a different time base than the second clock signal, a first crystal oscillator is arranged as the time base for the first clock signal and a second crystal oscillator is arranged as the time base for the second clock signal.
12. 12 . The method according to claim 1 , wherein a time base of the pseudo-random number generator is independent of the time base of a pulse width modulation frequency generation.
13. 13 . The method according to claim 1 , wherein a time base of the pseudo-random number generator is asynchronous with a time base of a pulse width modulation frequency generation.
14. 14 . The method according to claim 1 , wherein the generating including generating the pulse width modulation frequency by the pseudo-random number generator for a respective time duration, a reciprocal value of the time duration is greater than the resonant frequency.
15. 15 . The method according to claim 1 , the series circuit is always switched off when an intermediate circuit voltage falls below a threshold value.
16. 16 . The method according to claim 1 , wherein the series circuit is switched on when an intermediate circuit voltage exceeds a first threshold value.
17. 17 . The method according to claim 1 , wherein the series circuit is switched on when an intermediate circuit voltage exceeds a first threshold and if either no switch-on has previously taken place or a last switch-on was more than a determined time duration, the time duration T equaling a reciprocal value of the frequency.
18. 18 . The method according to claim 15 , wherein the series circuit is switched on when an intermediate circuit voltage exceeds a first threshold value, the first threshold value being greater than the second threshold value.
19. 19 . The method according to claim 1 , wherein a counter counting down from a respective start value in time with a first clock signal determines a pulse width modulation period duration, a pseudo-random number generator operated in time with a second clock signal generates the start value, a first time base feeds the first clock signal to the counter, and a second time base feeds a second clock signal to the counter.
20. 20 . The method according to claim 19 , wherein the second time base is independent of the first time base, the first time base being asynchronous with the second time base, the first clock signal being asynchronous with the second clock signal.

Description

FIELD OF THE INVENTION The present invention relates to a method for operating a drive system, and a drive system for carrying out a method. BACKGROUND INFORMATION In certain conventional systems, a drive system has an electric motor fed by an inverter. German Patent Document No. 10 2019 005 019 describes a method for operating a drive system. An electric vehicle drive is described in U.S. Patent Application Publication No. 2010/0332065. An electromotive drive system is described in Japanese Patent Document No 2019-30044. A converter is described in Chinese Patent Document No. 1242536. A power converter is described in Japanese Patent Document No. 2020-188636. SUMMARY Example embodiments t of the present invention provide a drive system that is environmentally friendly. According to an example embodiment of the present invention, in a method for operating a drive system, which has a rectifier and at least one inverter with an electric motor, the electric motor is connected to the AC-side connection of the inverter, the DC-side connection of the inverter is connected to the DC-side connection of the rectifier via an inductance, e.g., a line inductance, a capacitance is connected to the DC-side connection of the inverter and/or to the DC-side connection of the rectifier, e.g., a non-polar capacitor, a film capacitor, etc., a respective series circuit respectively formed from a resistor and a controllable semiconductor switch, i.e., a braking chopper, is connected to the DC-side connection of the inverter and/or to the DC-side connection of the rectifier, the braking chopper, in the time period in which the braking chopper is operated, is operated with a pulse width modulation frequency f which is spaced apart from the resonant frequency of the oscillating circuit, e.g., resonant circuit, formed from the inductance and the capacitance or capacitances, and the pulse width modulation frequency f is determined by a pseudo-random number generator, e.g., for a respective time duration. Thus, noise emissions are reduced when the braking resistor is in operation. This is because the timing change of the pulse width modulation frequency prevents a resonance frequency from rising and the emitted sound is also less disturbing for people. Overall, the radiated energy is more widely distributed in the frequency range than when operating with just a single pulse width modulation frequency. Since the braking chopper is not only operated by the pseudo-random number generator as a function of time, but the operating times are also dependent on the DC voltage, e.g., the intermediate circuit voltage, environmental protection is further improved. This is because noise emissions are reduced. In addition, the risk of exciting a resonant frequency of an electrical oscillation can be reduced. According to example embodiments, the pulse width modulation frequency f is spaced apart from harmonic oscillations, e.g., harmonics, of the resonant frequency of the oscillating circuit, e.g., resonant circuit, formed from the inductance and the capacitance or capacitances. Thus, there is no excitation of an electrical oscillation in the intermediate circuit. According to example embodiments, the pulse width modulation period duration, i.e., the reciprocal value of the pulse width modulation frequency, is determined by the counting down of a counter loaded with a start value at the beginning of the pulse width modulation period, carried out in time with a first clock signal, and the start value is determined by the pseudo-random number generator. For example, the pseudo-random number generator operates in time with a second clock signal. Thus, noise emissions are reduced, thereby improving environmental protection. According to example embodiments, the pseudo-random number generator has a shift register fed back via a logic element. For example, the logic element supplies a non-vanishing start value to the shift register upon switch-on, and thereafter, for example, during further operation, the result of a logical link of output signals of the shift register is fed to the input of the shift register. Thus, ready, cost-effective implementation is possible. According to example embodiments, the pseudo-random number generator has flip-flops, e.g., toggle flip-flops, e.g., T-flip-flops, connected in series, whose clock inputs are synchronously supplied with the same clock signal, e.g., with the second clock signal, and whose outputs are fed to a counter as a start value, e.g., a start value represented digitally in parallel, e.g., after the counter has previously counted down to one and/or when the counter is started, and outputs of the flip-flops are fed to a logic element whose output is fed to the input of a first of the flip-flops connected in series. Thus, ready, cost-effective implementation is possible. According to example embodiments, the logical link is an EXOR link, e.g., an exclusive-OR link, or is composed only of EXOR links, e.g., ex