US-12620934-B2 - Envelope-detector-less forward data receiving device

US12620934B2US 12620934 B2US12620934 B2US 12620934B2US-12620934-B2

Abstract

An embodiment includes a forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, and includes: an input module configured to receive the ASK modulation signal as an input; a resonance regulating rectifier module configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation module configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier module includes a comparison unit configured to generate a gate signal for controlling on/off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal.

Inventors

Hyung-Min Lee
Hyun-Su Lee

Assignees

KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

Dates

Publication Date: 20260505
Application Date: 20250313
Priority Date: 20240418

Claims (8)

1 . A forward data receiving device that demodulates and receives an Amplitude Shift Keying (ASK) modulation signal, the device comprising: an input circuit configured to receive the ASK modulation signal as an input; a resonance regulating rectifier circuit configured to regulate and rectify an input voltage of the ASK modulation signal on the basis of Pulse Width Modulation (PWM) according to a preset target voltage, and apply a regulated voltage through an output transistor; and a demodulation circuit based on a digital logic circuit, configured to demodulate the ASK modulation signal according to a trend in a change of the input voltage compared to the regulated voltage, wherein the resonance regulating rectifier circuit includes a comparison circuit configured to generate a gate signal for controlling on/off of the output transistor, and generate a sample signal for demodulating the ASK modulation signal according to the trend in the change of the input voltage compared to the regulated voltage.
2 . The device according to claim 1 , wherein the demodulation circuit includes: a digital cleaner circuit configured to generate a clean signal by removing a resonant frequency noise of the ASK modulation signal from the sample signal; and a synchronization circuit configured to synchronize the clean signal according to the resonant frequency and a data rate of the ASK modulation signal.
3 . The device according to claim 2 , wherein the resonance regulating rectifier circuit further includes a conversion circuit configured to convert the input voltage into a half-wave voltage, and branch the input voltage into a path of a first input voltage and a path of a second input voltage, wherein the comparison circuit includes: a first comparison circuit configured to generate a first gate signal and a first sample signal for controlling on/off of a first output transistor corresponding to the path of the first input voltage; and a second comparison circuit configured to generate a second gate signal and a second sample signal for controlling on/off of a second output transistor corresponding to the path of the second input voltage.
4 . The device according to claim 3 , wherein the digital cleaner circuit includes: a first frequency divider configured to output a first frequency division signal as the first sample signal is applied; a second frequency divider configured to output a second frequency division signal as the second sample signal is applied; a first adder configured to output a first sum signal by adding the first frequency division signal and the second frequency division signal; a delay cell configured to output a delay signal as the first sum signal is input; a second adder configured to output a second sum signal by adding the first sum signal and the delay signal; a third adder configured to output a third sum signal by adding the first sample signal and the second sample signal; and a fourth adder configured to output the clean signal by adding the third sum signal and the second sum signal.
5 . The device according to claim 3 , wherein the synchronization circuit includes: a first clock generator configured to generate a first clock signal having the resonant frequency from the first input voltage and the second input voltage; a starter configured to generate a start signal when the clean signal becomes ‘1’; a second clock generator configured to generate, when the start signal is generated, a second clock signal that becomes a rising edge and has the resonant frequency when the clean signal becomes ‘1’; a first synchronizer configured to generate a first synchronization signal, which is a clean signal synchronized with the second clock signal, using the second clock signal and the clean signal as inputs; a frequency divider configured to divide the second clock signal by frequency; a delayer configured to generate a signal having a pulse width of the resonant frequency by delaying the frequency-divided second clock signal for a preset cycle; and a second synchronizer configured to finally output a second synchronization signal synchronized with the resonant frequency and the data rate using an output signal of the delayer and the first synchronization signal as inputs as a demodulation signal that demodulates the ASK modulation signal.
6 . The device according to claim 3 , wherein each of the first comparison circuit and the second comparison circuit includes: a common gate comparator configured to compare the first input voltage or the second input voltage with the regulated voltage, and output a comparison voltage signal, which is a section in which the first input voltage or the second input voltage is higher than the regulated voltage; and a sample signal generator configured to generate a sample signal, which is a signal that includes information on a starting point and an ending point of the comparison voltage signal such that a pulse signal has a rising edge at the starting point and a falling edge at the ending point of the comparison voltage signal.
7 . The device according to claim 6 , wherein each of the first comparison circuit and the second comparison circuit further includes: a PWM controller configured to generate a PWM control signal by comparing the regulated voltage and the target voltage so that the regulated voltage follows the target voltage; and a gate signal driver configured to generate a gate signal for controlling on/off of the output transistor according to the comparison voltage signal and the PWM control signal.
8 . The device according to claim 7 , wherein the gate signal driver includes: an OR gate configured to generate a protection voltage signal by applying an OR logic operation to a signal applying a rising edge trigger to the PWM control signal and a signal applying a rising edge trigger to the ending point of the comparison voltage signal; and an SR latch configured to receive a signal applying a falling edge trigger at the starting point of the comparison voltage signal and the protection voltage signal, and generating the gate signal having a falling edge at the starting point of the comparison voltage signal and a rising edge at a timing of controlling the regulated voltage.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application claims priority to Korean Patent Application No. 10-2024-0052317, filed on Apr. 18, 2024, in the Korean Intellectual Property Office, which is incorporated by reference herein in its entirety. FIELD OF THE INVENTION The present invention relates to a forward data receiving device that does not require an envelope detector, which is implemented using only digital circuits to reduce power consumption. BACKGROUND OF THE RELATED ART Techniques of supplying power through Wireless Power Transfer (WPT), which supplies power wirelessly instead of supplying power through wires in electronic devices, are emerging. Such a wireless power transfer system may transmit and receive power through change in the magnetic field of coils at both ends of transmitting and receiving sides. The receiving side is mostly in a single-stage structure configured of an AC-DC rectifier and a DC-DC converter. The AC-DC rectifier converts AC voltage into DC voltage, and at this point, the DC voltage is not set to a target voltage value, but varies according to the distance between the coils and the angle and the load (RL) of the coils through feedback. Therefore, the DC-DC converter is essential at the rear end, and may convert unstable DC voltage into stable DC voltage through feedback. In addition, this stable DC voltage may be regulated according to the goal of a consumer and designer, and almost does not change according to the distance between the coils and the angle and the load of the coils. FIG. 1 is a view showing a conventional resonance regulating rectifier, and FIG. 2 is a view for explaining conventional voltage width modulation (hereinafter, referred to as PWM) technology. As shown in FIG. 1, recently, resonance regulating rectifiers that reduce a two-stage structure to a single-stage structure are used widely. Such one-stage resonance regulating rectifiers have advantages of high power conversion efficiency, a high voltage conversion rate, and a small chip area. In addition, in order to convert AC voltage into a stable target DC voltage using a single-stage structure, PWM technology is used as shown in FIG. 2. The PWM technology reduces the width of gate voltage when the target voltage is low, and increases the width of gate voltage when the target voltage is high. In addition, such a resonance regulating rectifier may transmit wireless power from a transmitter TX to a receiver RX via a pair of coils L1 and L2 as shown in FIG. 1, and may also transmit data from a transmitter TX to a receiver RX or from a receiver RX to a transmitter TX. At this point, it is general that sending data from a transmitter TX to a receiver RX is referred to as forward telemetry (FT or downlink), and sending data from a receiver RX to a transmitter TX is referred to as backward telemetry (BT or uplink). Meanwhile, FIG. 3 is a view showing an FT Amplitude Shift Keying (ASK), which is a method of a conventional amplitude phase modulator. Specifically, FIG. 3a is a view showing a circuit diagram of conventional ASK FT, and FIG. 3b is a view showing a waveform of ASK FT. The conventional ASK FT method is configured of an FT demodulator including an envelope detector and an analog comparator as shown in FIG. 3. In addition, the cross-coupled NMOS pair N1 and N2 converts a full-wave voltage to half-wave voltages VIN1 and VIN2. In addition, half of the current in the power path flows from VIN1 to VREG through a first power pass PMOS transistor P1 controlled by a first gate control voltage VG1. In the same manner, the other half of the current in the power path is directed from VIN2 to VREG through a second PMOS transistor P2 by controlling a second gate control voltage VG2. At this point, the envelope detector is configured of PMOS transistors P3 and P4 connected through a diode, a storage capacitor CENV, and a current path resistor RENV. This envelope detector looks like another type of rectifier, and requires another current for the FT path, as well as the WPT. The auxiliary current of the FT path is formed from VINN and VINP to GND through the PMOS transistors P3 and P4 and the current path resistance RENV, and this generates output voltage VENV of the envelope detector. The output voltage VENV decreases as VTX decreases, and the analog comparator detects the decrease and compares it with a reference voltage VREF to generate the digital output VFT of the demodulator. Since the output voltage VENV is generated by an RC-based envelope detector, decrease of the output voltage VENV varies according to the input data value and the data rate. In addition, since the magnitude of the capacitance CENV is usually 100 pF or more, and the capacitor occupies a significant part of the chip area, existing FT demodulators have a problem of consuming considerable power due to the envelope detector including the auxiliary power path and the analog comparator. Therefore, a method that can reduce the power consumpti