US-12620942-B2 - Bias circuit for stacked power amplifiers with a variable power supply

US12620942B2US 12620942 B2US12620942 B2US 12620942B2US-12620942-B2

Abstract

Stacked amplifier architectures that have bias circuits that are tolerant of supply voltage variations, which provide good reliability, are fast to follow V CC changes, and exhibit small variations in gain as V CC varies. One embodiment encompasses a bias circuit for an amplifier stack, including a source follower circuit configured to output a bias voltage to a transistor within the amplifier stack and configured to be coupled to a variable voltage, and a controller coupled to the source follower circuit, configured to be coupled to a constant voltage, and configured to apply a constant voltage to the source follower circuit. The source follower circuit generates a reference voltage and (1) outputs a constant bias voltage when the variable voltage is above the reference voltage, and (2) outputs a bias voltage proportional to the variable voltage when the variable voltage is below the reference voltage.

Inventors

Shota Ishihara
Rui Ma

Assignees

MURATA MANUFACTURING CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20230426

Claims (19)

1 . A bias circuit for an amplifier stack configured to be coupled to a variable voltage source, the bias circuit including: (a) a source follower circuit including an input terminal, an output terminal, and a control input, the source follower circuit configured to output a bias voltage on the output terminal when coupled to a gate of a transistor within the amplifier stack, and configured to have the input terminal be coupled to the variable voltage source for the amplifier stack; and (b) a controller coupled to the control input of the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the control input of the source follower circuit.
2 . The bias circuit of claim 1 , wherein the source follower circuit includes: (a) a source follower transistor having a conduction channel connected between the input terminal and the output terminal and configured to be coupled through the input terminal to the variable voltage source for the amplifier stack, the source follower transistor having a gate configured as the control input; (b) a first resistor coupled between the output terminal and a reference potential; and (c) a node between the output terminal and the resistor, the node configured to be coupled to the gate of the transistor within the amplifier stack.
3 . The bias circuit of claim 2 , wherein the controller includes: (a) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate; (b) a second resistor coupled to the conduction channel of the transistor; (c) a third resistor coupled between the second resistor and the reference potential; (d) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.
4 . The bias circuit of claim 3 , further including a capacitor coupled to the gate of the source follower transistor.
5 . The bias circuit of claim 2 , wherein the source follower circuit outputs a constant bias voltage when a voltage of the variable voltage source is above a gate reference voltage generated within the controller.
6 . The bias circuit of claim 2 , wherein the source follower circuit outputs a bias voltage proportional to a voltage of the variable voltage source when the voltage of the variable voltage source is below a gate reference voltage generated within the controller.
7 . The bias circuit of claim 2 , wherein the source follower circuit generates a gate reference voltage and (1) outputs a constant bias voltage when a voltage of the variable voltage source is above the gate reference voltage, and (2) outputs a bias voltage proportional to the voltage of the variable voltage source when the voltage of the variable voltage source is below the gate reference voltage.
8 . The bias circuit of claim 2 , wherein the source follower transistor is a MOSFET.
9 . A bias circuit for an amplifier stack, the bias circuit including: (a) a source follower circuit configured to output a bias voltage when coupled to a gate of a transistor within the amplifier stack, the source follower circuit configured to be coupled to a variable voltage source for the amplifier stack, wherein the source follower circuit includes: (1) a source follower transistor having a conduction channel configured to be coupled to the variable voltage source and having a gate; (2) a first resistor coupled between the conduction channel of the source follower transistor and a reference potential; and (3) an output between the source follower transistor and the resistor, the output configured to be coupled to the gate of the transistor within the amplifier stack; and (b) a controller coupled to the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the source follower circuit, wherein the controller includes: (1) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate; (2) a second resistor coupled to the conduction channel of the transistor; (3) a third resistor coupled between the second resistor and the reference potential; (4) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.
10 . The bias circuit of claim 9 , further including a capacitor coupled to the gate of the source follower transistor.
11 . An amplifier, including: (a) an amplifier stack comprising at least two series-connected FETs and configured to be coupled to a variable voltage source; (b) a bias circuit for the amplifier stack, the bias circuit including, for at least one FET within the amplifier stack: (1) a source follower circuit including an input terminal, an output terminal coupled to a gate of the at least one FET, and a control input, the source follower circuit configured to have the input terminal be coupled to the variable voltage source for the amplifier stack and to output a bias voltage on the output terminal to the gate of the at least one FET; and (2) a controller coupled to the control input of the source follower circuit, configured to be coupled to a constant voltage source, and configured to apply a constant voltage to the control input of the source follower circuit.
12 . The amplifier of claim 11 , wherein the source follower circuit includes: (a) a source follower transistor having a conduction channel connected between the input terminal and the output terminal and configured to be coupled through the input terminal to the variable voltage source for the amplifier stack, the source follower transistor having a gate configured as the control input; (b) a first resistor coupled between the output terminal and a reference potential; and (c) a node between the output terminal and the resistor, the node configured to be coupled to the gate of the at least one FET within the amplifier stack.
13 . The amplifier of claim 12 , wherein the controller includes: (a) a transistor having a conduction channel configured to be coupled to the constant voltage source and having a gate; (b) a second resistor coupled to the conduction channel of the transistor; (c) a third resistor coupled between the second resistor and the reference potential; (d) an operational amplifier having a first input coupled to a node between the second and third resistors, a second input coupled to a reference voltage, and an output coupled to the gate of the transistor and to the gate of the source follower transistor.
14 . The amplifier of claim 13 , further including a capacitor coupled to the gate of the source follower transistor.
15 . The amplifier of claim 11 , wherein the source follower circuit outputs a constant bias voltage when a voltage of the variable voltage source is above a gate reference voltage generated within the controller.
16 . The amplifier of claim 11 , wherein the source follower circuit outputs a bias voltage proportional to a voltage of the variable voltage source when the voltage of the variable voltage source is below a gate reference voltage generated within the controller.
17 . The amplifier of claim 11 , wherein the source follower circuit generates a gate reference voltage and (1) outputs a constant bias voltage when a voltage of the variable voltage source is above the gate reference voltage, and (2) outputs a bias voltage proportional to the voltage of the variable voltage source when the voltage of the variable voltage source is below the gate reference voltage.
18 . The amplifier of claim 11 , wherein the source follower transistor is a MOSFET.
19 . The amplifier of claim 11 , wherein at least one FET within the amplifier stack is coupled to and biased by a resistive ladder bias circuit.

Description

BACKGROUND (1) Technical Field The invention relates to electronic circuits, and more particularly to bias circuits for power amplifiers. (2) Background Amplifiers are a common component in electronic circuits, particularly in radio frequency (RF) transmitters and receivers. For many RF systems, particularly those requiring portability (e.g., cellular telephones, WiFi-connected computers, cameras, and other devices, etc.), it has become common to use complementary metal-oxide-semiconductor (CMOS) fabrication technology to create low cost, low power, complex integrated circuits (ICs) containing multiple field-effect transistors (FETs). FIG. 1 is a simplified schematic diagram of a first prior art amplifier circuit 100. The illustrated circuit 100 has a cascode common source architecture constructed from an amplifier stack 102 comprising at least two series-connected FETs M1-Mn, where n≥2. An input signal may be applied through an input port PIN coupled through an input impedance matching network 104 to the gate of a first or bottom FET M1 FET within the amplifier stack 102. The gate of FET M1 is also coupled to a voltage source Vg1_bias 106 through a resistor Rg1. The drain of FET M1 is coupled to (and thus drives) the source of a second FET M2. The source of MI is coupled to RF ground (in some embodiments, through a degeneration inductor circuit, not shown). Each FET in the stack above FET M1 has a source coupled to a lower-numbered FET and a drain coupled to a higher-numbered FET (except for the last or top FET Mn). The drain of FET Mn provides an amplified output signal to an output load and impedance matching network 108, which provides a modified amplified output signal at an output port POUT. Power is supplied to the amplifier circuit 100 from a DC voltage source VCC. Each FET M2-Mn includes a respective gate resistor Rg2-Rgn, each of which is coupled to a respective node within a bias circuit 110 comprising a resistive ladder of bias resistors Rb1-Rbn series-connected between VCC and circuit ground. The bias circuit 110 in combination with the gate resistors Rg2-Rgn provide respective voltages Vg2-Vgn to the FETs M2-Mn. FIG. 2 is a simplified schematic diagram of a second prior art amplifier circuit 200. Similar in most aspects to the amplifier circuit 100 of FIG. 1, the bias circuit 110 is connected between a constant voltage source VCON (rather than VCC) and circuit ground. While the cascode circuits 100, 200 illustrated in FIGS. 1 and 2 provide good isolation because there is no direct coupling from the input to the output, the circuits are not well suited to applications in which the DC supply voltage VCC varies, such as when a battery loses power over time or in applications where the DC supply voltage at the drain of FET Mn is actively modified to optimize operation at different power levels; examples include average power tracking (APT), envelope tracking (ET), and GSM power amplifier power control. In these examples, the supply voltage VCC may have a range that varies by a factor of 10 or more (e.g., from 4.5V to 0.4V, as one example). For example, FIG. 3 is a graph of gate voltage (Vg) as a function of VCC for two FETs M2, M5 in an embodiment of the prior art amplifier circuit 100 of FIG. 1 in which n=5 for the amplifier stack 102. As shown, the gate voltages Vg2 and Vg5 for the selected FETs vary directly with changes in VCC (the gate voltages Vg3 and Vg4 would be intermediate between Vg2 and Vg5). This behavior provides good reliability by keeping the gate-to-drain voltage VGD for each FET in the amplifier stack 102 small across variations of VCC, and the amplifier circuit 100 responds quickly to variations in VCC, which is good for such applications as envelope tracking. However, the amplifier circuit 100 exhibits a large variation in gain between high values of VCC and mid-to-low values of VCC (see also FIG. 8 below). As another example, FIG. 4 is a graph of Vg as a function of VCC for two FETs M2, M5 in an embodiment of the prior art amplifier circuit 200 of FIG. 2 in which n=5 for the amplifier stack 102. As shown, the gate voltages Vg2 and Vg5 for the selected FETs are essentially constant with respect to variations in VCC (the gate voltages Vg3 and Vg4 would be intermediate between Vg2 and Vg5). This behavior essentially eliminates large variations in gain as VCC varies, and the amplifier circuit 200 responds quickly to variations in VCC. However, the amplifier circuit 200 exhibits bad reliability, since the difference between a constant Vg5 (e.g., 4.5V) and a low value of VCC (e.g., 2.0V) may cause the VGD for FET M5 (2.5V in this example) to exceed the design capability of the FET, possibly leading to device failure. Other bias circuits 110 have been proposed that exhibit small variations in gain between high values of VCC and mid-to-low values of VCC and good reliability (small VGD even at low values of VCC), but which are slow to follow VCC changes. Accordingly, there is a need fo