US-12620979-B1 - Programmable digital oscillator

US12620979B1US 12620979 B1US12620979 B1US 12620979B1US-12620979-B1

Abstract

An example programmable digital oscillator includes digital oscillation circuitry and a digital-to-analog converter (DAC). The digital oscillation circuitry includes exactly one digital multiplier, exactly one digital adder, and exactly two registers. The digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code, where the programmable code is provided as input to the exactly one digital multiplier. The DAC is communicatively coupled to the digital oscillation circuitry and is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals.

Inventors

Zhiheng Wang
Seyednaser Mousavi
Ramesh Harjani

Assignees

REGENTS OF THE UNIVERSITY OF MINNESOTA

Dates

Publication Date: 20260505
Application Date: 20190830

Claims (20)

1 . A programmable digital oscillator, comprising: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, wherein the digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code, wherein the programmable code is provided as input to the exactly one digital multiplier, wherein the programmable code comprises a programmable hopping code, and wherein the digital oscillation circuitry is configured to provide the digital oscillation signals at the one or more frequencies as a function of the programmable hopping code; and a digital-to-analog converter (DAC) communicatively coupled to the digital oscillation circuitry, wherein the DAC is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals.
2 . The programmable digital oscillator of claim 1 , wherein the one digital multiplier includes a quantization noise source.
3 . The programmable digital oscillator of claim 1 , wherein: the exactly two registers include a first register and a second register, the first register is electrically coupled to the second register, the exactly one digital multiplier is electrically coupled to the exactly one digital adder and to the each of the first and second registers, and the exactly one digital adder is electrically coupled to the exactly one digital multiplier and to each of the first and second registers.
4 . The programmable digital oscillator of claim 1 , wherein the digital oscillation circuitry provides the digital oscillation signals at the one or more frequencies in a range from 0 to fs/2 based on the programmable code, where fs is a sampling clock frequency for the digital oscillation circuitry.
5 . The programmable digital oscillator of claim 1 , further comprising: an injection-locked oscillator communicatively coupled to the DAC, wherein the injection-locked oscillator functions as a bandpass filter with respect to the analog oscillation signals.
6 . The programmable digital oscillator of claim 1 , wherein the digital oscillation circuitry is associated with a transfer function z −2 +r 2 z −1 +1=0, wherein r 2 represents the programmable code, and wherein z −1 and z −2 represent respective Z transforms.
7 . A digital oscillator system, comprising: a plurality of digital oscillators including a first digital oscillator and a second digital oscillator, wherein each digital oscillator of the plurality of digital oscillators comprises: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, wherein the digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code of the respective digital oscillator, and wherein the programmable code is provided as input to the exactly one digital multiplier; and a digital-to-analog converter (DAC) communicatively coupled to the digital oscillation circuitry, wherein the DAC is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals, wherein the first digital oscillator is configured to output first analog oscillation signals of the analog oscillation signals, and wherein the second digital oscillator is configured to output second analog oscillation signals of the analog oscillation signals; and coupling circuitry that is configured to communicatively couple the first analog oscillation signals with a first carrier data stream that is received or transmitted via wireless communication channels within a first wireless channel range, and couple the second analog oscillation signals with a second carrier data stream that is received or transmitted via wireless communication channels within a second wireless channel range that is different from the first wireless channel range, wherein the first and second carrier data streams are aggregated via one or more aggregated data pipes to provide an aggregated bandwidth for the first and second carrier data streams.
8 . The digital oscillator system of claim 7 , wherein the wireless communication channels comprises radio frequency channels.
9 . The digital oscillator system of claim 7 , wherein the first and second carrier data streams are output to one or more mobile devices.
10 . The digital oscillator system of claim 7 , wherein the first and second carrier data streams comprise Long-Term Evolution (LTE) data streams, wherein the first wireless channel range and the second wireless channel range comprises a 20 MHz channel range, and wherein the aggregated bandwidth comprises a 100 MHz aggregated bandwidth.
11 . The programmable digital oscillator of claim 7 , wherein for each digital oscillator of the plurality of digital oscillators: the exactly two registers include a first register and a second register, the first register is electrically coupled to the second register, the exactly one digital multiplier is electrically coupled to the exactly one digital adder and to the each of the first and second registers, and the exactly one digital adder is electrically coupled to the exactly one digital multiplier and to each of the first and second registers.
12 . The digital oscillator system of claim 7 , wherein the programmable code comprises a programmable hopping code, wherein each digital oscillator of the plurality of digital oscillators is further communicatively coupled to transmitter correlation circuitry that is configured to spread, based on the respective analog oscillation signals, one or more transmit signals across multiple channels within the respective wireless channel range to create frequency-hopped transmit signals; and wherein each digital oscillator of the plurality of digital oscillators is further communicatively coupled to receiver correlation circuitry that is configured to de-spread one or more frequency-hopped data signals received via the respective wireless communication channels.
13 . The digital oscillator system of claim 7 , wherein each digital oscillator of the plurality of digital oscillators further comprises an injection-locked oscillator communicatively coupled to the respective DAC, wherein the injection-locked oscillator functions as a bandpass filter with respect to the respective analog oscillation signals.
14 . A method of carrier aggregation, comprising: providing, by a first digital oscillator included in a plurality of digital oscillators, first analog oscillation signals; providing, by a second digital oscillator included in the plurality of digital oscillators, second analog oscillation signals, wherein each of the first and second digital oscillators comprises: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, wherein the digital oscillation circuitry is configured to provide respective digital oscillation signals at one or more frequencies as a function of a programmable code of the respective digital oscillator, and wherein the programmable code is provided as input to the exactly one digital multiplier; and a digital-to-analog converter (DAC) communicatively coupled to the digital oscillation circuitry, wherein the DAC is configured to convert the respective digital oscillation signals from the digital oscillation circuitry into respective analog oscillation signals; coupling, by coupling circuitry, the first analog oscillation signals with a first carrier data stream that is received or transmitted via wireless communication channels within a first wireless channel range; and coupling, by the coupling circuitry, the second analog oscillation signals with a second carrier data stream that is received or transmitted via wireless communication channels within a second wireless channel range that is different from the first wireless channel range, wherein the first and second carrier data streams are aggregated via one or more aggregated data pipes to provide an aggregated bandwidth for the first and second carrier data streams.
15 . The method of claim 14 , wherein the first and second carrier data streams comprise first and second Long-Term Evolution (LTE) data streams, wherein the first and second wireless channel ranges each comprises a 20 MHz channel range.
16 . The method of claim 15 , further comprising: coupling, by the coupling circuitry, third analog oscillation signals provided by third digital oscillator with a third carrier data stream that is received or transmitted via wireless communication channels within a third wireless channel range; coupling, by the coupling circuitry, fourth analog oscillation signals provided by fourth digital oscillator with a fourth carrier data stream that is received or transmitted via wireless communication channels within a fourth wireless channel range; coupling, by the coupling circuitry, fifth analog oscillation signals provided by fifth digital oscillator with a fifth carrier data stream that is received or transmitted via wireless communication channels within a fifth wireless channel range, wherein the third, fourth, and fifth wireless channel ranges each comprises a 20 MHz channel range, and wherein the first, second, third, fourth, and fifth carrier data streams are aggregated via the one or more aggregated data pipes to provide the aggregated bandwidth of 100 MHz.
17 . The method of claim 14 , wherein for each of the first and second digital oscillators: the exactly two registers include a first register and a second register, the first register is electrically coupled to the second register, the exactly one digital multiplier is electrically coupled to the exactly one digital adder and to the each of the first and second registers, and the exactly one digital adder is electrically coupled to the exactly one digital multiplier and to each of the first and second registers.
18 . A programmable digital oscillator, comprising: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, wherein the digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code, wherein the programmable code is provided as input to the exactly one digital multiplier, wherein the programmable code comprises a programmable, continuously changing ramp code, and wherein the digital oscillation circuitry is configured to provide the digital oscillation signals at the one or more frequencies as a function of the programmable, continuously changing ramp code; and a digital-to-analog converter (DAC) communicatively coupled to the digital oscillation circuitry, wherein the DAC is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals.
19 . The programmable digital oscillator of claim 18 , wherein the one digital multiplier includes a quantization noise source.
20 . The programmable digital oscillator of claim 18 , wherein: the exactly two registers include a first register and a second register, the first register is electrically coupled to the second register, the exactly one digital multiplier is electrically coupled to the exactly one digital adder and to the each of the first and second registers, and the exactly one digital adder is electrically coupled to the exactly one digital multiplier and to each of the first and second registers.

Description

This application claims the benefit of U.S. Provisional Application No. 62/725,924 filed Aug. 31, 2018, which is incorporated herein by reference in its entirety. GOVERNMENT INTEREST This invention was made with government support under HR0011-17-2-0001 awarded by the Defense Advanced Research Projects Agency (DARPA). The government has certain rights in the invention. TECHNICAL FIELD The present disclosure relates to oscillator circuitry and systems. BACKGROUND Various prior techniques have been implemented to generate custom signals, such as custom oscillation signals. For example, analog phase locked loop (PLL) (e.g., Integer N PLL's, fraction N PLL's) may be utilized to generate custom signals. In some cases, digital PLL's may also be utilized in generating these types of oscillation signals. Another popular approach in generating custom signals is via the use of direct digital synthesis (DDS). SUMMARY The present disclosure describes techniques for implementing a digital oscillator (e.g., digital sine-wave oscillator) that has lower circuit complexity, lower power consumption, and higher-speed operation. This digital oscillator may include a combination of only one multiplier and one integrator. In various examples, the output frequency of the digital oscillator may be programmable, and may, in some cases, be centered around, e.g., fs/4, where fs is the sampling clock frequency. In various non-limiting examples, the output frequency of the digital oscillator can go anywhere between 0 to fs/2, based on the programmable code. The output of the digital oscillator, may also be converted to an analog value using an on-chip digital-to-analog converter. The digital oscillator described herein may be used in various applications, such as radar applications and carrier aggregation applications. In one example, a programmable digital oscillator includes digital oscillation circuitry and a digital-to-analog converter (DAC). The digital oscillation circuitry includes exactly one digital multiplier, exactly one digital adder, and exactly two registers. The digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code, where the programmable code is provided as input to the exactly one digital multiplier. The DAC is communicatively coupled to the digital oscillation circuitry and is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals. In one example, a method includes providing, by digital oscillation circuitry of a programmable digital oscillator, digital oscillation signals at one or more frequencies as a function of a programmable code, wherein the digital oscillation circuitry includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, and wherein the programmable code is provided as input to the exactly one digital multiplier. The example method further includes converting, by a digital-to-analog converter (DAC) of the programmable digital oscillator that is communicatively coupled to the digital oscillation circuitry, the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals. In one example, a digital oscillator system includes a plurality of digital oscillators. Each digital oscillator of the plurality of digital oscillators includes: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exactly two registers, wherein the digital oscillation circuitry is configured to provide digital oscillation signals at one or more frequencies as a function of a programmable code of the respective digital oscillator, and wherein the programmable code is provided as input to the exactly one digital multiplier; and a digital-to-analog converter (DAC) communicatively coupled to the digital oscillation circuitry, wherein the DAC is configured to convert the digital oscillation signals from the digital oscillation circuitry into analog oscillation signals. The digital oscillator system further includes coupling circuitry that is configured to communicatively couple the analog oscillation signals output by each digital oscillator of the plurality of digital oscillators with a respective data stream of a plurality of data streams, wherein each respective data stream is received or transmitted via wireless communication channels within a respective wireless channel range. In one example, a method of carrier aggregation includes providing, by a first digital oscillator included in a plurality of digital oscillators, first analog oscillation signals, and providing, by a second digital oscillator included in the plurality of digital oscillators, second analog oscillation signals. Each of the first and second digital oscillators comprises: digital oscillation circuitry that includes exactly one digital multiplier, exactly one digital adder, and exac