US-12620980-B2 - Multi-modulus divider

US12620980B2US 12620980 B2US12620980 B2US 12620980B2US-12620980-B2

Abstract

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

Inventors

Tu-I Tsai
Taeho SEONG

Assignees

QUALCOMM INCORPORATED

Dates

Publication Date: 20260505
Application Date: 20240208

Claims (11)

1 . A multi-modulus divider comprising: a prescaler comprising a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value; a finite state machine; a first flip-flop, wherein a data input of the first flip-flop is coupled to an output of the prescaler, and wherein an output of the first flip-flop is coupled to an input of the finite state machine; a second flip-flop, wherein a data input of the second flip-flop is coupled to the finite state machine such that the data input of the second flip-flop is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit; and a third flip-flop, wherein a data input of the third flip-flop is coupled to an output of the second flip-flop, and wherein an output of the third flip-flop is coupled to the combinational logic circuit.
2 . The multi-modulus divider of claim 1 , wherein a longest flop-to-flop delay is a summation of a first delay associated with the first flip-flop and a second delay associated with the second flip-flop.
3 . The multi-modulus divider of claim 1 , wherein the input clock signal has a frequency that is greater than 7 Gigahertz (GHz).
4 . The multi-modulus divider of claim 1 , wherein the first flip-flop, the second flip-flop, and the third flip-flop each comprise a delay (D) flip-flop.
5 . The multi-modulus divider of claim 1 , wherein a clock input of the first flip-flop and a clock input of the third flip-flop are configured to receive the input clock signal.
6 . The multi-modulus divider of claim 1 , wherein the finite state machine includes the second flip-flop.
7 . The multi-modulus divider of claim 1 , wherein: the first value is a first integer, and the second value is a second integer that is different than the first integer.
8 . The multi-modulus divider of claim 1 , wherein the prescaler further comprises a plurality of flip-flops, each of the plurality of flip-flops including a data input coupled to the combinational logic circuit and an output coupled to the combinational logic circuit.
9 . The multi-modulus divider of claim 8 , wherein the data input of the first flip-flop is coupled to the output of one of the plurality of flip-flops of the prescaler.
10 . The multi-modulus divider of claim 1 , wherein the output of the first flip-flop is coupled to a clock input of the second flip-flop.
11 . A phase-locked loop (PLL) circuit comprising the multi-modulus divider of claim 1 .

Description

TECHNICAL FIELD Certain aspects of the present disclosure generally relate to electronic circuits and, more particularly, to multi-modulus dividers, which may be used in frequency synthesizers, for example. BACKGROUND Wireless communication devices are widely deployed to provide various communication services such as telephony, video, data, messaging, broadcasts, and so on. Such wireless communication devices may transmit and/or receive radio frequency (RF) signals via any of various suitable radio access technologies (RATs) including, but not limited to, 5G New Radio (NR), Long Term Evolution (LTE), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Wideband CDMA (WCDMA), Global System for Mobility (GSM), Bluetooth, Bluetooth Low Energy (BLE), ZigBee, wireless local area network (WLAN) RATs (e.g., WiFi), and the like. A wireless communication network may include a number of base stations that can support communication for a number of mobile stations. A mobile station (MS) may communicate with a base station (BS) or other wireless network node via a downlink and an uplink. The downlink (or forward link) refers to the communication link from the base station to the mobile station, and the uplink (or reverse link) refers to the communication link from the mobile station to the base station. A base station may transmit data and control information on the downlink to a mobile station and/or may receive data and control information on the uplink from the mobile station. The base station and/or mobile station may include at least one frequency synthesizer to generate and control a local oscillator (LO) signal for mixing with a baseband signal (or a radio frequency (RF) signal) for upconversion (or downconversion) to an intermediate frequency (IF) signal or an RF signal (or an IF signal or a baseband signal) before transmission (after reception). SUMMARY The systems, methods, and devices of the disclosure each have several aspects, no single one of which is solely responsible for its desirable attributes. Without limiting the scope of this disclosure as expressed by the claims which follow, some features will now be discussed briefly. After considering this discussion, and particularly after reading the section entitled “Detailed Description,” one will understand how the features of this disclosure provide advantages that include using dedicated flip-flops between a prescaler of a multi-modulus divider and a finite state machine of the multi-modulus divider to improve performance (e.g., relaxed flip flop speeds) of the multi-modulus divider at certain frequencies (e.g., above 7 Gigahertz) by eliminating a delay associated with the prescaler of the multi-modulus divider. Certain aspects of the present disclosure provide a multi-modulus divider. The multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit. Certain aspects of the present disclosure provide a method of clock signal generation. The method generally includes synchronizing, via a first flip-flop, an output signal generated by a prescaler; providing the synchronized output signal to a finite state machine; synchronizing, via a second flip-flop, a programming signal output by the finite state machine, wherein the programming signal is associated with programming a combinational logic circuit of the prescaler; providing the synchronized programming signal to a third flip-flop; resynchronizing, via the third flip-flop, the synchronized programming signal; and providing the resynchronized programming signal to the combinational logic circuit of the prescaler. To the accomplishment of the foregoing and related ends, the one or more aspects comprise the features hereinafter fully described and particularly pointed out in the claims. The following description and the annexed drawings set forth in detail certain illustrative features of the one or more aspects. These features are indicative, however, of but a few of the various ways in which the principles of various aspects may be employed, and this description is intended to include all such aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS So that the manner in which the above-recit