US-12620983-B2 - Half-bridge circuit for two-wire buses

Abstract

The present disclosure relates to a half-bridge circuit comprising first and second PMOS transistors in series between the first node and an intermediate node, a third PMOS transistor and a fourth NMOS transistor in series between the intermediate node and the second node, and a control circuit. The control circuit comprises a bootstrap charge pump. The charge pump comprises a capacitive element having a first electrode coupled with the gate of the third transistor. The charge pump is configured to charge the capacitive element from the intermediate node and without a clock signal. The present application also relates to a device comprising two identical half-bridge circuits connected to two respective conductors of a bus.

Inventors

• Denis Cottin

Assignees

• STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date

20260505

Application Date

20240619

Priority Date

20230705

Claims (20)

1. 1 . A half-bridge circuit comprising: a first P-channel metal-oxide-semiconductor (PMOS) transistor having its drain connected to a first node for applying a power supply potential and its source connected to its body region; a second PMOS transistor having its source connected to its body region and to the source of the first PMOS transistor, and its drain connected to an intermediate node; a third PMOS transistor having its drain connected to the intermediate node and its source connected to its body region; a fourth N-channel metal-oxide-semiconductor (NMOS) transistor having its drain connected to the source of the third PMOS transistor and its source connected to a second node for applying a reference potential; and a control circuit of the third PMOS transistor comprising a bootstrap charge pump, the bootstrap charge pump comprising a capacitive element having a first electrode coupled with a gate of the third PMOS transistor, the bootstrap charge pump being configured to charge the capacitive element from the intermediate node and without a clock signal.
2. 2 . The half-bridge circuit according to claim 1 , wherein the capacitive element has a second electrode coupled with the drain or the source of the third PMOS transistor, and the bootstrap charge pump comprises: a first diode having its anode coupled with the gate of the third PMOS transistor and its cathode coupled with the second node; and at least one of a resistor connected between the source and the gate of the third PMOS transistor, or a Zener diode connected between the source and the gate of the third PMOS transistor with its anode at a gate-side.
3. 3 . The half-bridge circuit according to claim 2 , wherein: the second electrode of the capacitive element is coupled with the source of the third PMOS transistor; and the bootstrap charge pump comprises the Zener diode connected between the source and the gate of the third PMOS transistor.
4. 4 . The half-bridge circuit according to claim 2 , wherein: the second electrode of the capacitive element is coupled with the drain of the third PMOS transistor.
5. 5 . The half-bridge circuit according to claim 2 , wherein the control circuit further comprises a first switch coupling the first diode with the second node, the control circuit being configured to control the first switch from a first binary signal.
6. 6 . The half-bridge circuit according to claim 5 , wherein the first binary signal is at least in part determined from an enabling/disabling signal for enabling/disabling the half-bridge circuit so that the first switch is open in response to the enabling/disabling signal indicating the half-bridge circuit has to be disable.
7. 7 . The half-bridge circuit according to claim 5 , wherein the first switch is implemented by a NMOS transistor having its source connected to its body region, its drain coupled with the first diode, and its source coupled with the second node.
8. 8 . The half-bridge circuit according to claim 5 , wherein: the half-bridge circuit further comprises a detection circuit configured to deliver a second binary signal indicating that a potential of the intermediate node is less than the reference potential; and the first binary signal is determined at least in part from the second binary signal so that the first switch of the control circuit is open in response to the second binary signal indicating that the potential at the intermediate node is less than the reference potential.
9. 9 . The half-bridge circuit according to claim 8 , wherein the control circuit is configured to drive the gate of the third PMOS transistor to a supply voltage in response to the second binary signal indicating that the potential at the intermediate node is less than the reference potential.
10. 10 . The half-bridge circuit according to claim 9 , wherein the control circuit further comprises a second switch coupling the gate of the third PMOS transistor with the first node, and a second resistor coupling the gate of the third PMOS transistor with the anode of the first diode, the control circuit being configured to turn the second switch to an ON state in response to the second binary signal indicating that the potential at the intermediate node is less than the reference potential.
11. 11 . The half-bridge circuit according to claim 10 , wherein: the second switch comprises: two PMOS transistors in series between the first node and the gate of the third PMOS transistor and having sources connected to each other; and a third resistor coupling each gate of the two PMOS transistors with the sources of the two PMOS transistors; the control circuit further comprises a third switch, for example a NMOS transistor, coupling gates of its two PMOS transistors with the second node; and the control circuit is configured to turn its third switch to the ON state in response to the second binary signal indicating that the potential at the intermediate node is less than the reference potential.
12. 12 . The half-bridge circuit according to claim 8 , wherein the detection circuit configured to deliver the second binary signal comprises: two identical resistors in series between the first and second nodes, wherein a third node interconnecting the two identical resistors with each other is configured to deliver a reference voltage; a fourth resistor and a fifth resistor connected to a fourth node, the fourth resistor being connected between the first node and the fourth node, the fifth resistor having a value higher than the fourth resistor and being connected between the fourth node and the intermediate node; a fourth PMOS transistor connected between the first node and the fourth node, and having its source and gate connected to the first node; a fourth NMOS transistor connected between the fourth node and the second node and having its source and gate connected to the second node, the fourth node being configured to deliver a first voltage; and a comparator configured to compare the first voltage with the reference voltage, and to deliver the second binary signal.
13. 13 . The half-bridge circuit according to claim 1 , wherein the half-bridge circuit further comprises a first control circuit of the first PMOS transistor configured to turn the first PMOS transistor to an ON state in response to the second PMOS transistor being ON.
14. 14 . The half-bridge circuit according to claim 1 , wherein the half-bridge circuit further comprises: a detection circuit configured to deliver a third signal indicating that a potential at the intermediate node is higher than the power supply potential; and a first control circuit of the first PMOS transistor configured to: turn the first PMOS transistor to an ON state in response to the second PMOS transistor being ON and the third signal indicating that the potential at the intermediate node is less than the power supply potential; and turn the first PMOS transistor to an OFF state in response to the third signal indicating that the potential at the intermediate node is higher than the power supply potential.
15. 15 . The half-bridge circuit according to claim 12 , wherein the half-bridge circuit further comprises: a second detection circuit configured to deliver a third signal indicating that the potential at the intermediate node is higher than the power supply potential; and a first control circuit of the first PMOS transistor configured to: turn the first PMOS transistor to an ON state in response to the second PMOS transistor being ON and the third signal indicating that the potential at the intermediate node is less than the power supply potential; and turn the first PMOS transistor to an OFF state in response to the third signal indicating that the potential at the intermediate node is higher than the power supply potential; and wherein the second detection circuit configured to deliver the third signal comprises: a sixth resistor and a seventh resistor connected to a fifth node, the sixth resistor being connected between the intermediate node and the fifth node, the seventh resistor having a second value lower than the sixth resistor and being connected between the fifth and second nodes; a fifth PMOS transistor connected between the first node and the fifth node and having its source and gate connected to the first node; a fifth NMOS transistor connected between the second node and the fifth node and having its source and gate connected to the second node, the fifth node being configured to deliver a second voltage; and a second comparator configured to compare the second voltage with the reference voltage, and to deliver the third signal.
16. 16 . The half-bridge circuit according to claim 1 , further comprising a second control circuit of the second PMOS and fourth NMOS transistors configured to: control the OFF state of the fourth transistor and the ON state of the second PMOS transistor in response to a write control signal being at a first state; control the OFF state of the second PMOS transistor and the ON state of the fourth transistor in response to the write control signal being at a second state; and control the OFF state of each of the second PMOS and fourth NMOS transistors in response to the write control signal being at a third state.
17. 17 . A device comprising: first and second terminals configured to be respectively connected to first and second lines of a two-wire bus; and two identical half-bridge circuits, each of the identical half-bridge circuits comprising: a first P-channel metal-oxide-semiconductor (PMOS) transistor having its drain connected to a first node for applying a power supply potential and its source connected to its body region; a second PMOS transistor having its source connected to its body region and to the source of the first PMOS transistor, and its drain connected to an intermediate node; a third PMOS transistor having its drain connected to the intermediate node and its source connected to its body region; a fourth N-channel metal-oxide-semiconductor (NMOS) transistor having its drain connected to the source of the third PMOS transistor and its source connected to a second node for applying a reference potential; and a control circuit of the third PMOS transistor comprising a bootstrap charge pump, the bootstrap charge pump comprising a capacitive element having a first electrode coupled with a gate of the third PMOS transistor, the bootstrap charge pump being configured to charge the capacitive element from the intermediate node and without a clock signal; wherein a first half-bridge circuit of the two identical half-bridge circuits has its intermediate node connected to the first terminal; and wherein a second half-bridge circuit of the two identical half-bridge circuits has its intermediate node connected to the second terminal.
18. 18 . The device according to claim 17 , wherein, for each half-bridge circuit, the capacitive element has a second electrode coupled with the drain or the source of the third PMOS transistor, and the bootstrap charge pump further comprises: a first diode having its anode coupled with the gate of the third PMOS transistor and its cathode coupled with the second node; and at least one of a resistor connected between the source and the gate of the third PMOS transistor, or a Zener diode connected between the source and the gate of the third PMOS transistor with its anode at a gate-side.
19. 19 . The device according to claim 17 , wherein each half-bridge circuit further comprises a first control circuit of the first PMOS transistor configured to turn the first PMOS transistor to an ON state in response to the second PMOS transistor being ON.
20. 20 . The device according to claim 17 , wherein each half-bridge circuit further comprises: a detection circuit configured to deliver a third signal indicating that a potential at the intermediate node is higher than the power supply potential; and a first control circuit of the first PMOS transistor configured to: turn the first PMOS transistor to an ON state in response to the second PMOS transistor being ON and the third signal indicating that the potential at the intermediate node is less than the power supply potential; and turn the first PMOS transistor to an OFF state in response to the third signal indicating that the potential at the intermediate node is higher than the power supply potential.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the priority benefit of French patent application no. 2307153, filed on Jul. 5, 2023, entitled “Half-bridge circuit for two-wire buses,” which is hereby incorporated herein by reference to the maximum extent allowable by law. TECHNICAL FIELD The present description relates generally to electronic circuits, for example integrated electronic circuits. More particularly, the present description relates to a device configured to be connected to a two-wire bus in order to transmit digital data or bits. BACKGROUND ART Systems comprising a two-wire bus, i.e., a bus consisting of two conductive lines on which bits are transmitted with devices connected to the two-wire bus, are known. Among these known systems, some systems include two-wire differential bus, for example systems including a R5-485-type bus. On a differential bus, the useful signal corresponds to the voltage between the two conductive lines of the bus, i.e., the differential voltage of the bus. To control the differential voltage of the bus, the devices connected to the differential two-wire bus each include a bus write circuit, also known as a driver. Known circuits (or devices) for writing to a differential two-wire bus have their drawbacks. SUMMARY There is a need to overcome some or all of the drawbacks of two-wire bus devices, and in particular devices for writing to a differential two-wire bus. For example, there is a need for a device for writing to a differential two-wire bus that increases the maximum value that the differential voltage of the bus can take, compared with known devices. For example, there is a need for such a device to be robust enough to withstand electrostatic discharges (ESD) on each of the conductive lines of the bus, for example 12 kV electrostatic discharges as defined by the International Electrotechnical Commission (IEC). For example, there is a need for such a device that also enables it to be robust to, i.e., withstand without damage, shifts in its reference voltage, for example GND, between this device and another similar device connected to the two-wire bus. One embodiment address some or all of the drawbacks of known two-wire bus devices. In particular, one embodiment address some or all of the known devices for writing to a differential two-wire bus. For example, one embodiment provides a device for writing to a differential two-wire bus that enables the value of the differential voltage on the bus to be increased compared with similar known devices. For example, one embodiment provides for such a device to further withstand electrostatic discharges on either of the two bus conductor lines, for example 12 kV electrostatic discharges as defined by the International Electrotechnical Commission. For example, one embodiment provides for such a device to further withstand reference voltage offsets of the device relative to other similar devices connected to the two-wire bus. For example, one embodiment provides such a device for use with an RS-485 type bus. One embodiment provides a half-bridge circuit comprising: a first PMOS transistor having its drain connected to a first node for applying a power supply potential and its source connected to its body region;a second PMOS transistor having its source connected to its body region and to the source of the first transistor, and its drain connected to an intermediate node;a third PMOS transistor having its drain connected to the intermediate node and its source connected to its body region;a fourth NMOS transistor having its drain connected to the source of the third transistor and its source connected to a second node for applying a reference potential; anda control circuit of the third transistor comprising a bootstrap charge pump, the charge pump comprising a capacitive element having a first electrode coupled with, preferably connected to, the gate of the third transistor, the charge pump being configured to charge the capacitive element from the intermediate node and without a clock signal. According to one embodiment: the capacitive element has a second electrode coupled with the drain or source of the third transistor; and the charge pump comprises:a first diode having its anode coupled with the gate of the third transistor and its cathode coupled with the second node, andat least one of a resistor connected between the source and the gate of the third transistor, and a Zener diode connected between the source and the gate of the third transistor with its anode at the gate side. According to one embodiment: the second electrode of the capacitive element is coupled with, preferably connected to, the source of the third transistor; andthe charge pump comprises the Zener diode connected between the source and the gate of the third transistor. According to one embodiment, the second electrode of the capacitive element is coupled with, preferably connected to, the drain of the third transistor. According