US-12620985-B2 - Low power consumption power-on reset system

US12620985B2US 12620985 B2US12620985 B2US 12620985B2US-12620985-B2

Abstract

A Power-on Reset (POR) system includes: an SR latch circuit, powered by a supply voltage, for generating a POR signal according to the supply voltage and an enable signal; and at least one operating circuit, powered by the supply voltage. At least one state circuit in the operating circuit is reset by the POR signal. When the supply voltage starts up, an output terminal of the SR latch circuit has a predetermined state, such that after the supply voltage starts up and before the enable signal is enabled for a first time, the POR signal is in a reset state to reset the at least one state circuit in the operating circuit. After the supply voltage starts up and the enable signal is enabled for the first time, the POR signal turns to a non-reset state, and the operating circuit is enabled to operate according to the enable signal.

Inventors

Tsung-Han Yang
Pao-Hsun Yu
Yung-Ming Chang

Assignees

RICHTEK TECHNOLOGY CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240522
Priority Date: 20240220

Claims (8)

1 . A power-on reset system comprising: an SR latch circuit, powered by a supply voltage and configured to generate a power-on reset signal according to the supply voltage and an enable signal, wherein an enablement or a disablement of the enable signal is unrelated to a rising edge or a falling edge of the supply voltage, wherein the enablement of the enable signal includes a first enablement of the enable signal; and at least one operating circuit, powered by the supply voltage and configured to reset at least one state circuit within each of the at least one operating circuit according to the power-on reset signal; wherein when the supply voltage starts up, an output terminal of the SR latch circuit is configured to have and keep at a predetermined state, such that after a start-up of the supply voltage and before the first enablement of the enable signal, the power-on reset signal is in a reset state to reset the at least one state circuit within each of the at least one operating circuit; wherein after the first enablement of the enable signal subsequent to the start-up of the supply voltage, the power-on reset signal turns to a non-reset state.
2 . The power-on reset system of claim 1 , wherein the SR latch circuit includes plural logic gates which include: a first logic gate and a second logic gate cross-coupled through feedback connections to each other, wherein the first logic gate receives a signal related to the enable signal, and the second logic gate receives a signal related to the supply voltage, wherein one of outputs of either the first logic gate or the second logic gate corresponds to the power-on reset signal.
3 . The power-on reset system of claim 2 , wherein each of the plural logic gates includes plural upper transistors and plural lower transistors complementarily coupled to each other, wherein conduction impedances of the plural upper transistors and the plural lower transistors in at least one of the first logic gate and the second logic gate are asymmetrical to an extent that the output terminal of the SR latch circuit has the predetermined state upon the start-up of the supply voltage.
4 . The power-on reset system of claim 2 , wherein the output terminal includes a positive output terminal and a negative output terminal, the power-on reset system further comprising: a pulling circuit configured to pull at least one of the positive output terminal and the negative output terminal to a corresponding predetermined voltage upon the start-up of the supply voltage, such that the output terminal of the SR latch circuit has the predetermined state.
5 . The power-on reset system of claim 4 , wherein the pulling circuit is configured to pull the positive output terminal to a first predetermined voltage, and/or to pull the negative output terminal to a second predetermined voltage, wherein the first predetermined voltage and the second predetermined voltage are complementary.
6 . The power-on reset system of claim 5 , wherein the pulling circuit includes a pulling component coupled to either the positive output terminal or the negative output terminal for pulling the respective terminal to the corresponding predetermined voltage, wherein the pulling component includes: an enhancement-mode MOS transistor controlled to be non-conductive; a depletion-mode MOS transistor controlled to be non-conductive; or a resistor.
7 . The power-on reset system of claim 2 , wherein each of the first logic gate and the second logic gate is either a NOR gate or a NAND gate.
8 . The power-on reset system of claim 1 , wherein the power-on reset signal remains in the non-reset state until the supply voltage is turned off, wherein during the non-reset state of the power-on reset signal, the operating circuit is further configured to operate when the enable signal is enabled and to cease operating when the enable signal is disabled.

Description

CROSS REFERENCE The present invention claims priority to TW patent application Ser. No. 113106036, filed on Feb. 20, 2024. BACKGROUND OF THE INVENTION Field of Invention The present invention relates to a power-on reset system. Particularly it relates to a low power consumption power-on reset system. Description of Related Art FIG. 1A shows a block diagram of a power-on reset system of prior art. As shown in FIG. 1A, in the power-on reset system 9000 of prior art, both the power-on reset circuit 910 and the operating circuit 920 are powered by the supply voltage VCC. The power-on reset circuit 910 generates a power-on reset signal POR′ based on the supply voltage VCC. The operating circuit 920 resets plural SR latch circuits within the operating circuit 920 according to the power-on reset signal POR′. FIGS. 1B and 1C show schematic diagrams of the power-on reset circuit of prior art. The power-on reset circuit 910 of FIG. 1A can be configured as the power-on reset circuit 911 of FIG. 1B or the power-on reset circuit 912 of FIG. 1C. As shown in FIG. 1B, the power-on reset circuit 911 includes a resistor Rs, a capacitor C and an inverter 9111. The inverter 9111 generates the power-on reset signal POR′ based on the signal Sig at the joint node between the resistor Rs and the capacitor C. As shown in FIG. 1C, the power-on reset circuit 912 includes a reference signal generation circuit 9121 and a comparator 9122. The comparator 9122 generates the power-on reset signal POR′ based on the reference signal Vref generated by the reference signal generation circuit 9121 and the supply voltage VCC. FIG. 2 shows an operation waveform diagram corresponding to the power-on reset system of prior art in FIGS. 1A and 1B. One drawback of the prior art is that when the power-on reset circuit 910 of FIG. 1A is configured as the power-on reset circuit 911 of FIG. 1B, if the level of the supply voltage VCC ramps up slowly, the level of the power-on reset signal POR′ will be too low to enter the reset state (e.g., high state), causing the plural SR latch circuits within the operating circuit 920 to also fail to enter the reset state. Another drawback of the prior art is that when the power-on reset circuit 910 of FIG. 1A is configured as the power-on reset circuit 912 of FIG. 1C, the power-on reset system is inefficient due to excessive power consumption. In view of this, the present invention addresses the deficiencies of the prior art by proposing a low power consumption power-on reset system. The power-on reset system of the present invention, through the special design of the power-on reset circuit, not only reduces power consumption but also ensures that the level of the power-on reset signal can continue to keep ramping up, even when the level of the supply voltage ramps up slowly, to enter the reset state, thereby achieving the reset operation of the power-on reset circuit on the operating circuit. SUMMARY OF THE INVENTION From one perspective, the present invention provides a power-on reset system comprising: an SR latch circuit, powered by a supply voltage and configured to generate a power-on reset signal according to the supply voltage and an enable signal; and at least one operating circuit, powered by the supply voltage and configured to reset at least one state circuit within each of the at least one operating circuit according to the power-on reset signal; wherein when the supply voltage starts up, an output terminal of the SR latch circuit is configured to have and keep at a predetermined state, such that after a start-up of the supply voltage and before a first enablement of the enable signal, the power-on reset signal is in a reset state to reset the at least one state circuit within each of the at least one operating circuit; wherein after the first enablement of the enable signal subsequent to the start-up of the supply voltage, the power-on reset signal turns to a non-reset state. In one preferred embodiment, the SR latch circuit includes plural logic gates which include: a first logic gate and a second logic gate cross-coupled through feedback connections to each other, wherein the first logic gate receives a signal related to the enable signal, and the second logic gate receives a signal related to the supply voltage, wherein one of outputs of either the first logic gate or the second logic gate corresponds to the power-on reset signal. In one preferred embodiment, each of the plural logic gates includes plural upper transistors and plural lower transistors complementarily coupled to each other, wherein the conduction impedances of the plural upper transistors and the plural lower transistors in at least one of the first logic gate and the second logic gate are asymmetrical to an extent that the output terminal of the SR latch circuit has the predetermined state upon the start-up of the supply voltage. In one preferred embodiment, the output terminal includes a positive output terminal and a negative output