US-12620986-B2 - Device for monitoring one or a plurality of power supplies

US12620986B2US 12620986 B2US12620986 B2US 12620986B2US-12620986-B2

Abstract

A circuit comprises first, second, and third nodes ( 2002, 2004, 2006 ) respectively receiving a reference potential, a first voltage, and a second voltage. A first NMOS transistor has its gate connected to the second node. A second NMOS transistor has its drain and its source respectively connected to the source of the first transistor and to the second node. A third NMOS transistor has its gate and its source respectively connected to the second and first nodes. A fourth PMOS transistor has its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor. A resistive element connects the first transistor to the third node, another resistive element connecting the fourth transistor to the third node.

Inventors

Anass Samir
Bastien Giraud
Sébastien RICAVY

Assignees

Commissariat à l'Energie Atomique et aux Energies Alternatives

Dates

Publication Date: 20260505
Application Date: 20240814
Priority Date: 20230818

Claims (12)

1 . Circuit comprising: a first node configured to receive a reference potential; a second node configured to receive a first DC voltage, the first DC voltage being a power supply voltage; a third node configured to receive a second DC voltage; a first NMOS transistor having its gate connected to the second node; a second NMOS transistor having its drain connected to the source of the first transistor and its source connected to the second node; a third NMOS transistor having its gate connected to the second node and its source connected to the first node; a fourth PMOS transistor having its drain connected to the drain of the third transistor and to the gate of the second transistor and its gate connected to the source of the first transistor; a first resistive element connected between the drain of the first transistor and the third node; a second resistive element connected between the source of the fourth transistor and the third node; and a first CMOS inverter configured to be powered with the second voltage, an input of the first inverter being connected to the drain of the third transistor and an output of the first inverter being configured to deliver a reset signal.
2 . Circuit according to claim 1 , wherein each of the first and second resistive elements is implemented by a PMOS transistor having its gate connected to the first node and its source connected to the third node.
3 . Circuit according to claim 1 , further comprising a capacitive element connected between the gate and source of the first transistor.
4 . Circuit according to claim 1 , further comprising a second CMOS inverter configured to be powered with the second voltage, an input of the second inverter being connected to the output of the first inverter, and an output of the second inverter being configured to deliver a signal complementary to the reset signal.
5 . Circuit according to claim 1 , wherein the first and second resistive elements, and the first and fourth transistors are sized so that the fourth transistor is off when the first transistor is on.
6 . Circuit according to claim 1 , wherein the second voltage also is a power supply voltage.
7 . Device comprising: at least one circuit according to claim 1 , and a voltage generation circuit configured to deliver the second DC voltage at a non-zero value before a powering on and a ramping up of the first voltage, the non-zero value being preferably adapted to allowing a switching to the on state of the fourth transistor from the powering on of the first voltage.
8 . Device comprising: at least two circuits according to claim 1 ; a voltage generation circuit configured to deliver the second DC voltage at a non-zero value before a powering on and a ramping up of the first voltage, the non-zero value being preferably adapted to allowing a switching to the on state of the fourth transistor from the powering on of the first voltage; the device comprises a CMOS logic gate configured to implement a Boolean AND logic function between the reset signals delivered by said at least two circuits, wherein: the first nodes of said at least two circuits are configured to receive the same reference potential; the third nodes of said at least two circuits are configured to receive the second voltage delivered by the voltage generation circuit, said second voltage being a reference voltage; and the second nodes of said at least two circuits are each configured to receive a first DC power supply voltage different from the first voltages received by the second nodes of the other circuits.
9 . Device according to claim 8 , wherein the CMOS logic gate is configured to be powered with the second voltage delivered by the voltage generation circuit.
10 . Device according to claim 8 , wherein the voltage generation circuit is configured to deliver the second DC reference voltage at its nominal value prior to the powering on and the ramping up of each of the first voltages.
11 . Device according to claim 8 , wherein the circuit for generating the second reference voltage comprises: a first voltage dividing bridge connected between a first power supply node configured to receive one of the first DC power supply voltages and a second power supply node configured to receive the reference potential; a first MOS transistor and a second resistive voltage dividing bridge connected in series between the first and second power supply nodes, the first transistor having its gate connected to an intermediate node of the first bridge and its source connected to the second power supply node; a first buffer circuit configured to be powered with said one of the first DC power supply voltages and comprising an input connected to a first intermediate node of the second bridge and an output configured to deliver the second reference voltage; and a second MOS transistor having its drain connected to the output of the first buffer circuit and its source connected to the first power supply node, wherein the first bridge is configured so that the first transistor is off when said one of the first DC power supply voltages is at a value lower than a first threshold, itself lower than a breakdown voltage of the transistors, and wherein the second transistor is configured to be in the on state if the first transistor is off, and conversely.
12 . Device according to claim 8 , wherein the circuit for generating the second reference voltage comprises: a first voltage dividing bridge connected between a first power supply node configured to receive one of the first DC power supply voltages and a second power supply node configured to receive the reference potential; a first MOS transistor and a second resistive voltage dividing bridge connected in series between the first and second power supply nodes, the first transistor having its gate connected to an intermediate node of the first bridge and its source connected to the first power supply node; a second MOS transistor and a third resistive voltage dividing bridge connected in series between the first and second power supply nodes, the source of the second MOS transistor being connected to the second power supply node; a buffer circuit configured to be powered with said one of the first DC power supply voltages and comprising an input connected to a first intermediate node of the third bridge and an output configured to deliver the second reference voltage; and a third MOS transistor having its drain connected to the output of the buffer circuit and its source connected to the first power supply node; wherein the second transistor is configured to be in the off, respectively on, state when the first transistor is in the off, respectively on, state, wherein the third transistor is configured to be in the on state if the second transistor is in the off state, and conversely, and wherein the first bridge is configured so that the first transistor is off when said one of the first DC power supply voltages is at a value lower than a first threshold, itself lower than a breakdown voltage of the transistors.

Description

FIELD The present disclosure generally concerns the monitoring of one or a plurality of power supply voltages, and more particularly power-on reset (POR) strategies. BACKGROUND Known chips more and more often comprise a plurality of power supply voltage domains and/or portions of the chip with circuits using a plurality of power supply voltages. When a power supply voltage is turned off, it is in a high-impedance state. When it is turned on, or powered on, this power supply voltage first has a zero value, before reaching its nominal or target value at the end of a ramp-up phase. During the powering on and the ramping up of one or a plurality of power supply voltages of a portion of the chip, many problems arise in circuits which receive this or these power supply voltages in order to be powered. Known circuits generate, during the ramping up of one or a plurality of power supply voltages, a reset signal which enables to set the circuits to be powered with this or these power supply voltage(s) to a known initial state. However, these known power-on reset circuits have many disadvantages. SUMMARY There exists a need for a power-on reset circuit which overcomes all or part of the disadvantages of known power-on reset circuits. For example, there exists a need for a power-on reset circuit which consumes less power than known power-on reset circuits. For example, there exists a need for a power-on reset device which is independent from the ramp-up sequence of the power supply voltages that it monitors. For example, there exists a need for a power-on reset device which delivers a reset signal having a defined state as soon as one of the power supply voltages monitored by the device is turned on and is no longer in a high-impedance state. For example, there exists a need for a power-on reset device which allows an implementation with MOS (Metal Oxide Semiconductor) transistors having a breakdown voltage Vmax, while one of the power supply voltages monitored by this device has a nominal value higher than this breakdown voltage Vmax and/or the difference in values between two of the voltages monitored by the device may be greater than this breakdown voltage Vmax. An embodiment overcomes all or part of the disadvantages of known power-on reset circuits and devices. An embodiment provides a circuit comprising: a first node configured to receive a reference potential;a second node configured to receive a first DC voltage, the first DC voltage being a power supply voltage;a third node configured to receive a second DC voltage;a first NMOS transistor having its gate connected to the second node;a second NMOS transistor having its drain connected to the source of the first transistor and its source connected to the second node;a third NMOS transistor having its gate connected to the second node and its source connected to the first node;a fourth PMOS transistor having its drain connected to the drain of the third transistor and to the gate of the second transistor, and its gate connected to the source of the first transistor;a first resistive element connected between the drain of the first transistor and the third node;a second resistive element connected between the source of the fourth transistor and the third node; anda first CMOS inverter configured to be powered with the second voltage, an input of the first inverter being connected to the drain of the third transistor and an output of the first inverter being configured to deliver a reset signal. According to an embodiment, each of the first and second resistive elements is implemented by a PMOS transistor having its gate connected to the first node and its source connected to the third node. According to an embodiment, the circuit further comprises a capacitive element connected between the gate and the source of the first transistor. According to an embodiment, the circuit further comprises a second CMOS inverter configured to be powered with the second voltage, an input of the second inverter being connected to the output of the first inverter, and an output of the second inverter being configured to deliver a signal complementary to the reset signal. According to an embodiment, the first and second resistive elements and the first and fourth transistors are sized so that the fourth transistor is off when the first transistor is on. According to an embodiment, the second voltage is also a power supply voltage. Another embodiment provides a device comprising: at least one circuit such as defined above, anda voltage generation circuit configured to deliver the second DC voltage at a non-zero value prior to a powering on and a ramping up of the first voltage, the non-zero value being preferably adapted to allowing a switching to the on state of the fourth transistor from the powering-on of the first voltage. According to an embodiment: said at least one circuit comprises at least two circuits such as described hereabove;the device comprises a CMOS logic gate config