US-12620988-B2 - Gate voltage bootstrap switching circuit

US12620988B2US 12620988 B2US12620988 B2US 12620988B2US-12620988-B2

Abstract

A gate voltage bootstrap switching circuit includes an LDO, a first MOS transistor, a second MOS transistor, a third MOS transistor, and a voltage control unit. The LDO has an inverting input terminal of connected to its output terminal. Drain of the first MOS transistor and source of the third MOS transistor are connected to the output terminal, source of the first MOS transistor is connected to drain of the second MOS transistor, and source of the second MOS transistor is connected to drain of the third MOS transistor. Capacitor arrays are connected. The voltage control unit is connected to gates of the first, second, and third MOS transistors to input an external power supply voltage as a gate-source voltage to the MOS transistors. The circuit eliminates the non-linearity of the impedance of the switch MOS transistors and improves the conversion speed of the ADC.

Inventors

Lun Wang
Xiangyang Guo

Assignees

IPGOAL MICROELECTRONICS (SICHUAN) CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20241215
Priority Date: 20240531

Claims (7)

1 . A gate voltage bootstrap switching circuit, adapted for a common mode voltage sampling structure, comprising a low dropout regulator (LDO), a first MOS transistor, a second MOS transistor, a third MOS transistor, and a voltage control unit; wherein a non-inverting input terminal of the LDO is connected to an external reference voltage, an inverting input terminal of the LDO is connected to an output terminal of the LDO which outputs a common mode voltage; a drain of the first MOS transistor and a source of the third MOS transistor are both connected to the output terminal of the LDO, a source of the first MOS transistor is connected to a drain of the second MOS transistor, and a source of the second MOS transistor is connected to a drain of the third MOS transistor; two external capacitor arrays are connected to the source and drain of the second MOS transistor, respectively; the voltage control unit is connected to an external power supply, and further connected to gates of the first, second, and third MOS transistors respectively to input a voltage of the external power supply as a gate-source voltage to the first, second, and third MOS transistors.
2 . The gate voltage bootstrap switching circuit according to claim 1 , wherein the first, second, and third MOS transistors are all N-type MOS transistors.
3 . The gate voltage bootstrap switching circuit according to claim 2 , wherein a width-to-length ratio of the first, second, and third MOS transistors is greater than 100.
4 . The gate voltage bootstrap switching circuit according to claim 1 , wherein the voltage control unit comprises a fourth MOS transistor, a fifth MOS transistor, a sixth MOS transistor, a seventh MOS transistor, an eighth MOS transistor, a ninth MOS transistor, a tenth MOS transistor, an eleventh MOS transistor, a twelfth MOS transistor, and a first capacitor; a gate of the fourth MOS transistor, a gate of the sixth MOS transistor, a source of the fifth MOS transistor, and a drain of the ninth MOS transistor are all connected to a gate of the second MOS transistor; a drain of the fourth MOS transistor is connected to the output terminal of the LDO, a source of the fourth MOS transistor is connected to a drain of the twelfth MOS transistor, a source of the eighth MOS transistor, and one end of the first capacitor; a drain of the fifth MOS transistor is connected to the other end of the first capacitor and a drain of the sixth MOS transistor; a gate of the fifth MOS transistor is connected to a drain of the eighth MOS transistor and a source of the seventh MOS transistor, a source of the ninth MOS transistor is connected to a source of the tenth MOS transistor and a drain of the eleventh MOS transistor, and the sources of the ninth MOS transistor and the tenth MOS transistor are both grounded; the external power supply is connected to a source of the sixth MOS transistor, a drain of the seventh MOS transistor, a gate of the ninth MOS transistor, and a drain of the tenth MOS transistor; a first external clock signal is input to the gates of the tenth MOS transistor, the eleventh MOS transistor, and the twelfth MOS transistor, respectively; and a second external clock signal is input to the gates of the seventh MOS transistor and the eighth MOS transistor, respectively.
5 . The gate voltage bootstrap switching circuit according to claim 4 , wherein the first external clock signal and the second external clock signal have a same frequency and opposite phases.
6 . The gate voltage bootstrap switching circuit according to claim 4 , wherein a width-to-length ratio of the fourth MOS transistor is greater than 60.
7 . The gate voltage bootstrap switching circuit according to claim 4 , wherein a capacitance value of the first capacitor is greater than 1 pF.

Description

FIELD OF THE INVENTION The present invention relates to the field of integrated circuits, and more specifically to a gate voltage bootstrap switching circuit. BACKGROUND OF THE INVENTION In the design of the successive approximation analog-to-digital converter (SAR ADC), the design of the internal digital-to-analog converter (DAC) is crucial. The DAC is primarily used to sample the input signal with low error and generate two voltages for comparison, which are then compared by a comparator to obtain a digital level for analog signal conversion. The part of the circuit that samples the input signal determines the accuracy of the input signal. If the sampling switch circuit is not sufficiently good, it may ultimately lead to a decrease in the effective bits of the digital signal output by the ADC. There are many common sampling structures for SAR ADCs, including traditional switch sampling structures, low-power capacitive switch sampling structures, and monotonic switch sampling structures. Currently, many SAR ADCs on the market with resolutions below 14 bits and sampling rates below 5M use traditional switch sampling structures, for example as shown the circuit structure of a 4-bit SAR ADC in FIG. 1. In the structure shown in FIG. 1, during sampling, switch S1 is closed, and the voltages Vpos and Vneg are the same. Switch S1 is a conventional complementary switch structure (as shown in FIG. 2), and the on-resistance Ron of switch S1 is given by: Ron=RonN//RonP. It's seen that, the N-type MOS switch parallel to the P-type MOS switch (as shown in FIG. 2, RonN is the equivalent resistance value of the N-type MOS transistor, and RonP is the equivalent resistance value of the P-type MOS transistor). It's calculated that, Ron=1μn⁢Cox(WL)N⁢(VDD-Vin-Vthn)//1μp⁢Cox(WL)P⁢(Vin+Vthp), where the parameters μn, μp, Cox respectively represent a carrier mobility of the N-type MOS transistor, a carrier mobility of the P-type MOS transistor, and an unit capacitance of the gate oxide layer. VDD (not shown in the figure) represents a supply voltage, Vin represents a voltage of Vpos and Vneg during sampling, and Vthn and Vthp represents threshold voltages for turning on the N-type MOS transistor and the P-type MOS transistor, respectively. In the above quotation, since the voltage Vth is actually a function of the voltage Vin, the resistance Ron exhibits non-linearity, meaning that the resistance Ron changes with variations in voltage Vin. Furthermore, considering the non-linearity caused by charge injection, the switch S1 in FIG. 1 uses the transmission gate form switch (MOS switch) shown in FIG. 2. In this structure, the sizes of the P-type and N-type MOS transistors are the same to eliminate charge injection. Additionally, the MOS transistors require low resistance to not affect the sampling time. CT and CTN are control signals with the same frequency but opposite phases. In the above complementary switch structure, differential and single-ended configurations cannot share the same capacitor array. The capacitance required for single-ended mode is double that for differential mode, leading to increased capacitance values and areas, which in turn raises the power consumption and production costs of the overall circuit. Therefore, there is a need to provide an improved gate voltage bootstrap switching circuit to overcome the aforementioned defects in common mode voltage sampling structures. SUMMARY OF THE INVENTION The purpose of the present invention is to provide a gate voltage bootstrap switching circuit, which eliminates the non-linearity of the impedance of the switch MOS transistors and improves the conversion speed of the ADC. To achieve the above objectives, the present invention provides a gate voltage bootstrap switching circuit, adapted for a common mode voltage sampling structure, and the circuit includes a low dropout regulator (LDO), a first MOS transistor, a second MOS transistor, a third MOS transistor, and a voltage control unit. A non-inverting input terminal of the LDO is connected to an external reference voltage, an inverting input terminal of the LDO is connected to an output terminal of the LDO which outputs a common mode voltage; a drain of the first MOS transistor and a source of the third MOS transistor are both connected to the output terminal of the LDO, a source of the first MOS transistor is connected to a drain of the second MOS transistor, and a source of the second MOS transistor is connected to a drain of the third MOS transistor; two external capacitor arrays are connected to the source and drain of the second MOS transistor, respectively; the voltage control unit is connected to an external power supply, and further connected to gates of the first, second, and third MOS transistors respectively to input a voltage of the external power supply as a gate-source voltage to the first, second, and third MOS transistors. As a preferable embodiment, the first, second, and third MOS transistors are al