US-12620991-B2 - Semiconductor integrated circuit and receiver device

US12620991B2US 12620991 B2US12620991 B2US 12620991B2US-12620991-B2

Abstract

A semiconductor integrated circuit includes a first input terminal inputting a first signal, a second input terminal supplied to a first voltage, an output terminal outputting a second signal. The circuit includes: a first transistor having first, second, control terminals respectively connected to a first node, the output terminal and first input terminals; a second transistor having first, second, control terminals respectively connected to the first and second nodes, the output terminal; a third transistor having a first terminal supplied to a second voltage, second and control terminals respectively connected to the first node and the second input terminal; a fourth transistor having first and control terminals respectively connected to the output terminal and the second node, a second terminal supplied to a third voltage; and a fifth transistor having first and control terminals connected to the second node, and a second terminal supplied to the third voltage.

Inventors

Huy Cu NGO

Assignees

KIOXIA CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240307
Priority Date: 20230315

Claims (20)

1 . A semiconductor integrated circuit comprising a first buffer having a first input terminal to which a first signal is input, a second input terminal to which a first voltage is supplied, and a first output terminal from which a second signal is output, wherein the first buffer includes: a first transistor having a first terminal connected to a first node, a second terminal connected to the first output terminal, and a control terminal connected to the first input terminal; a second transistor having a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to the first output terminal; a third transistor having a first terminal to which a second voltage is supplied, a second terminal connected to the first node, and a control terminal connected to the second input terminal; a fourth transistor having a first terminal connected to the first output terminal, a second terminal to which a third voltage is supplied, and a control terminal connected to the second node; a fifth transistor having a first terminal and a control terminal each connected to the second node, and a second terminal to which the third voltage is supplied; and a sixth transistor or a third capacitor, the sixth transistor having a first terminal to which the second voltage is supplied, a second terminal connected to the first output terminal, and a control terminal connected to the first node, the third capacitor having a first terminal connected to the first node and a second terminal connected to the first output terminal.
2 . The semiconductor integrated circuit according to claim 1 , wherein the first buffer further has a third input terminal to which a third signal constituting differential signals with the first signal is input, and the first buffer further includes: a seventh transistor having a first terminal to which the second voltage is supplied, a second terminal connected to the first output terminal, and a control terminal connected to the third input terminal; and a first current source having an input terminal connected to the first output terminal and an output terminal to which the third voltage is supplied.
3 . The semiconductor integrated circuit according to claim 1 , further comprising a second buffer having a third input terminal to which a third signal constituting differential signals with the first signal is input, a fourth input terminal to which the first voltage is supplied, and a second output terminal from which a fourth signal constituting differential signals with the second signal is output, wherein the second buffer includes: an eighth transistor having a first terminal connected to a third node, a second terminal connected to the second output terminal, and a control terminal connected to the third input terminal; a ninth transistor having a first terminal connected to the third node, a second terminal connected to a fourth node, and a control terminal connected to the second output terminal; a tenth transistor having a first terminal to which the second voltage is supplied, a second terminal connected to the third node, and a control terminal connected to the fourth input terminal; an eleventh transistor having a first terminal connected to the second output terminal, a second terminal to which the third voltage is supplied, and a control terminal connected to the fourth node; and a twelfth transistor having a first terminal and a control terminal each connected to the fourth node, and a second terminal to which the third voltage is supplied.
4 . The semiconductor integrated circuit according to claim 3 , wherein the first buffer further includes a first capacitor having a first terminal connected to the second input terminal and a second terminal connected to the third node, and the second buffer further includes a second capacitor having a first terminal connected to the fourth input terminal and a second terminal connected to the first node.
5 . The semiconductor integrated circuit according to claim 3 , further comprising: a first converter configured to determine a first bit string from the second signal and the fourth signal based on a first clock signal; and a second converter configured to determine a second bit string from the second signal and the fourth signal based on a second clock signal shifted from the first clock signal by a first phase.
6 . The semiconductor integrated circuit according to claim 5 , wherein each of the first converter and the second converter is a successive approximation register AD converter.
7 . The semiconductor integrated circuit according to claim 1 , wherein the first transistor, the fourth transistor, and the fifth transistor have a first conductivity type, and the second transistor and the third transistor have a second conductivity type different from the first conductivity type.
8 . The semiconductor integrated circuit according to claim 7 , wherein the first conductivity type is an N-conductivity type, the second conductivity type is a P-conductivity type, and the second voltage is higher than the third voltage.
9 . The semiconductor integrated circuit according to claim 7 , wherein the first conductivity type is a P-conductivity type, the second conductivity type is an N-conductivity type, and the third voltage is higher than the second voltage.
10 . The semiconductor integrated circuit according to claim 1 , wherein the first buffer is a source follower.
11 . A receiver device comprising: the semiconductor integrated circuit according to claim 1 ; and a processing circuit configured to process a signal output from the semiconductor integrated circuit.
12 . The receiver device according to claim 11 , wherein the first buffer further has a third input terminal to which a third signal constituting differential signals with the first signal is input, and the first buffer further includes: a seventh transistor having a first terminal to which the second voltage is supplied, a second terminal connected to the first output terminal, and a control terminal connected to the third input terminal; and a first current source having an input terminal connected to the first output terminal and an output terminal to which the third voltage is supplied.
13 . The receiver device according to claim 11 , further comprising a second buffer having a third input terminal to which a third signal constituting differential signals with the first signal is input, a fourth input terminal to which the first voltage is supplied, and a second output terminal from which a fourth signal constituting differential signals with the second signal is output, wherein the second buffer includes: an eighth transistor having a first terminal connected to a third node, a second terminal connected to the second output terminal, and a control terminal connected to the third input terminal; a ninth transistor having a first terminal connected to the third node, a second terminal connected to a fourth node, and a control terminal connected to the second output terminal; a tenth transistor having a first terminal to which the second voltage is supplied, a second terminal connected to the third node, and a control terminal connected to the fourth input terminal; an eleventh transistor having a first terminal connected to the second output terminal, a second terminal to which the third voltage is supplied, and a control terminal connected to the fourth node; and a twelfth transistor having a first terminal and a control terminal each connected to the fourth node, and a second terminal to which the third voltage is supplied.
14 . The receiver device according to claim 13 , wherein the first buffer further includes a first capacitor having a first terminal connected to the second input terminal and a second terminal connected to the third node, and the second buffer further includes a second capacitor having a first terminal connected to the fourth input terminal and a second terminal connected to the first node.
15 . The receiver device according to claim 13 , further comprising: a first converter configured to determine a first bit string from the second signal and the fourth signal based on a first clock signal; and a second converter configured to determine a second bit string from the second signal and the fourth signal based on a second clock signal shifted from the first clock signal by a first phase.
16 . The receiver device according to claim 15 , wherein each of the first converter and the second converter is a successive approximation register AD converter.
17 . The receiver device according to claim 11 , wherein the first transistor, the fourth transistor, and the fifth transistor have a first conductivity type, and the second transistor and the third transistor have a second conductivity type different from the first conductivity type.
18 . The receiver device according to claim 17 , wherein the first conductivity type is an N-conductivity type, the second conductivity type is a P-conductivity type, and the second voltage is higher than the third voltage.
19 . The receiver device according to claim 17 , wherein the first conductivity type is a P-conductivity type, the second conductivity type is an N-conductivity type, and the third voltage is higher than the second voltage.
20 . The receiver device according to claim 11 , wherein the first buffer is a source follower.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from Japanese Patent Application No. 2023-041277, filed Mar. 15, 2023, the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a semiconductor integrated circuit and a receiver device. BACKGROUND A transmitter device and a receiver device are connected via a transmission path. The transmitter device superimposes data on an analog signal and outputs the analog signal. The receiver device receives the analog signal that has passed through the transmission path. The receiver device includes a semiconductor integrated circuit that processes the analog signal. The receiver device generates a digital signal based on the analog signal. The receiver device recovers the data based on the generated digital signal. BRIEF DESCRIPTION OF DRAWINGS FIG. 1 is a block diagram illustrating an example of a configuration of a communication system including a receiver device according to an embodiment. FIG. 2 is a block diagram illustrating an example of a configuration of a receiver circuit included in the receiver device according to the embodiment. FIG. 3 is a block diagram illustrating an example of a configuration of an AD converter included in the receiver circuit according to the embodiment. FIG. 4 is a block diagram illustrating an example of a configuration of a buffer included in the AD converter according to the embodiment. FIG. 5 is a circuit diagram illustrating an example of a configuration of the buffer included in the AD converter according to the embodiment. FIG. 6 is a circuit diagram illustrating an example of a configuration of a buffer included in an AD converter according to a modification. DETAILED DESCRIPTION In general, according to one embodiment, a semiconductor integrated circuit includes a first buffer having a first input terminal to which a first signal is input, a second input terminal to which a first voltage is supplied, and a first output terminal from which a second signal is output. The first buffer includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor has a first terminal connected to a first node, a second terminal connected to the first output terminal, and a control terminal connected to the first input terminal. The second transistor has a first terminal connected to the first node, a second terminal connected to a second node, and a control terminal connected to the first output terminal. The third transistor has a first terminal to which a second voltage is supplied, a second terminal connected to the first node, and a control terminal connected to the second input terminal. The fourth transistor has a first terminal connected to the first output terminal, a second terminal to which a third voltage is supplied, and a control terminal connected to the second node. The fifth transistor has a first terminal and a control terminal each connected to the second node, and a second terminal to which the third voltage is supplied. Embodiments will be described below with reference to the drawings. Note that, in the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. In a case where elements having similar configurations are particularly distinguished from each other, letters or numbers different from each other may be added to the ends of the same reference numerals. 1. Embodiment An embodiment will be described. 1.1 Communication System A configuration of a communication system including a receiver device according to the embodiment will first be described. FIG. 1 is a block diagram illustrating an example of a configuration of the communication system including the receiver device according to the embodiment. A communication system 1 is configured to transmit data from one device or circuit to another device or circuit by high-speed serial communication. Specifically, for example, the communication system 1 achieves a communication speed of 128 Gbps. The communication system 1 includes a transmitter device 2, a transmission path 3, and a receiver device 4. The communication system 1 may be constituted by a plurality of devices or circuits provided on the same printed circuit board, or may be constituted by a plurality of devices or circuits provided on different printed circuit board. The transmitter device 2 is configured to transmit signals TR and /TR to the receiver device 4 via the transmission path 3. The signals TR and /TR are differential signals. The signals TR and /TR are, for example, signals including a plurality of pulse signals. Data is superimposed on each pulse signal of the signals TR and /TR. The voltage level of each pulse signal of the signals TR and /TR corresponds to data of one or more bits. The data superimposed on the pulse signal is t