US-12620993-B1 - Ballistic superconducting circuit for asynchronous reversible logic element

US12620993B1US 12620993 B1US12620993 B1US 12620993B1US-12620993-B1

Abstract

A ballistic, asynchronous logic circuit includes a controlled barrier which has a reversible memory cell and a polarity filter. The polarity filter is inductively coupled to the reversible memory cell. The circuit includes first and second polarity separators connected to the controlled barrier. The circuit includes a circulator connected to the controlled barrier.

Inventors

Rupert M. Lewis
Michael P. Frank
Steven B. Kaplan

Assignees

NATIONAL TECHNOLOGY & ENGINEERING SOLUTIONS OF SANDIA, LLC

Dates

Publication Date: 20260505
Application Date: 20250204

Claims (20)

1 . A ballistic, asynchronous logic circuit comprising: a pair of control inputs; a pair control outputs; a pair of data inputs; a pair of data outputs; a pair of complementary data outputs; a first polarity separator having a pair of first terminals connected to the control inputs and having a pair of second terminals and a pair of third terminals; a circulator having a pair of first terminals connected to the pair of data inputs, a pair of second terminals connected to the pair of complementary data outputs and having a pair of third terminals; a second polarity separator having a pair of first terminals, a pair of second terminals connected to the second terminals of the first polarity selector and a pair of third terminals connected to the control outputs; and a superconducting controlled barrier having a pair of first terminals connected to the third terminals of the first polarity selector, a pair of second terminals connected to the third terminals of the circulator, a pair of third terminals connected to the first terminals of the second polarity selector and a pair of fourth terminals connected to the pair of complementary data outputs.
2 . The circuit of claim 1 , wherein the superconducting controlled barrier comprises: a reversible memory cell having a pair of first terminals connected to the third terminals of the first polarity separator and a pair of second terminals connected to the first terminals of the second polarity separator; and a polarity filter inductively coupled to the reversible memory cell and having a pair of first terminals connected to the third terminals of the circulator and a pair of second terminals connected to the pair of complementary data outputs.
3 . The circuit of claim 2 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
4 . The circuit of claim 2 , wherein the reversible memory cell comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor; a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
5 . The circuit of claim 2 , wherein the polarity filter comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a third inductor having first and second terminals; a fourth inductor having first and second terminals; a Josephson Junction comprising: a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor; a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
6 . The circuit of claim 1 , wherein: the pair of control inputs are configured to receive control input fluxons; and the pair control outputs are configured to provide control output fluxons.
7 . The circuit of claim 1 , wherein: the pair of data inputs are configured to receive input data fluxons; the pair of data outputs are configured to provide output data fluxons; and the pair of complementary data outputs are configured to provide complementary output data fluxons.
8 . A ballistic, asynchronous logic circuit comprising: a first polarity separator having a pair of first terminals coupled to receive to control input fluxons and having a pair of second terminals and a pair of third terminals; a circulator having a pair of first terminals coupled to receive to data input fluxons, a pair of second terminals configured to provide complementary output data fluxons and having a pair of third terminals; a second polarity separator having a pair of first terminals, a pair of second terminals connected to the second terminals of the first polarity separator and a pair of third terminals configured to provide control output fluxons; and a superconducting controlled barrier having a pair of first terminals connected to the third terminals of the first polarity selector, a pair of second terminals connected to the third terminals of the circulator, a pair of third terminals connected to the first terminals of the second polarity selector and a pair of fourth terminals configured to provide output data fluxons.
9 . The circuit of claim 8 , wherein the superconducting controlled barrier comprises: a reversible memory cell having a pair of first terminals connected to the third terminals of the first polarity separator and a pair of second terminals connected to the first terminals of the second polarity separator; and a polarity filter inductively coupled to the reversible memory cell and having a pair of first terminals connected to the third terminals of the circulator and a pair of second terminals configured to provide the complementary output data fluxons.
10 . The circuit of claim 9 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
11 . The circuit of claim 9 , wherein the reversible memory cell comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor; a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
12 . The circuit of claim 9 , wherein the polarity filter comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a third inductor having first and second terminals; a fourth inductor having first and second terminals; a Josephson Junction having a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor and having a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
13 . A superconducting controlled barrier comprising: a reversible memory cell comprising: a pair of first terminals configured to receive control fluxons and a pair of second terminals configured to receive ejected fluxons; and a polarity filter comprising: a pair of first terminals configured to receive input data fluxons; a pair of second terminals configured to provide output data fluxons, wherein the polarity filter is inductively coupled to the reversible memory cell.
14 . The controlled barrier of claim 13 , wherein a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter.
15 . The controlled barrier of claim 13 , wherein the reversible memory cell comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor; a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal.
16 . The controlled barrier of claim 13 , wherein the polarity filter comprises: a first inductor having first and second terminals; a second inductor having first and second terminals; a third inductor having first and second terminals; a fourth inductor having first and second terminals; a Josephson Junction comprising: a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor; a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor.
17 . The controlled barrier of claim 13 , wherein the controlled barrier is set to a blocking state by applying a control fluxon of negative polarity to the reversible memory cell.
18 . The controlled barrier of claim 13 , wherein the controlled barrier is set to a passing state by applying a control a fluxon of positive polarity to the reversible cell.
19 . The controlled barrier of claim 17 , wherein the polarity filter reflects data fluxons in the blocking state.
20 . The controlled barrier of claim 18 , wherein the polarity filter allows data fluxons to pass through in the passing state.

Description

STATEMENT OF GOVERNMENT INTEREST This invention was made with Government support under Contract No. DE-NA0003525 awarded by the United States Department of Energy/National Nuclear Security Administration. The U.S. Government has certain rights in the invention. BACKGROUND INFORMATION 1. Field The present disclosure relates generally to logic circuits, and more specifically to a ballistic superconducting circuit for an asynchronous logic element. 2. Background Logic circuits (e.g., AND gates, OR gates, NOR gates, XOR gates) form the foundation of digital circuits. Traditionally, logic circuits are implemented using semiconductor-based technologies, such as CMOS transistors. While these devices have been scaled successfully to nanometer dimensions, their continued evolution faces several challenges. Current CMOS-based logic circuits operate irreversibly, dissipating significant amounts of energy in the form of heat for bits of information processed. This results from the fundamental thermodynamic limits of irreversible computation, posing a barrier to further miniaturization and energy efficiency in high-performance computing systems. Also, the switching speed of conventional gates is limited by parasitic capacitance, resistance, and the inherent delay in charging and discharging these components. This impacts the performance of processors, especially as clock frequencies continue to increase. Ballistic superconducting circuits rely on superconducting properties of materials. These circuits use flux quanta or fluxons to represent logical states. Flux quanta or fluxons can propagate ballistically through a circuit. As such, these circuits can transfer information or signal without any significant dissipation. Despite their potential, the practical realization of ballistic superconducting circuits has been challenging. SUMMARY According to an illustrative embodiment, a ballistic, asynchronous logic circuit is provided. The circuit includes a pair of control inputs, a pair control outputs, a pair of data inputs, a pair of data outputs and a pair of complementary data outputs. The circuit includes a first polarity separator having a pair of first terminals connected to the control inputs and having a pair of second terminals and a pair of third terminals. The circuit includes a circulator having a pair of first terminals connected to the data inputs, a pair of second terminals connected to the complementary data outputs and having a pair of third terminals. The circuit includes a second polarity separator having a pair of first terminals, a pair of second terminals connected to the second terminals of the first polarity selector and a pair of third terminals connected to the control outputs. The circuit includes a superconducting controlled barrier having a pair of first terminals connected to the third terminals of the first polarity selector, a pair of second terminals connected to the third terminals of the circulator, a pair of third terminals connected to the first terminals of the second polarity selector and a pair of fourth terminals connected to the data outputs. In an illustrative embodiment, the superconducting controlled barrier includes a reversible memory cell having a pair of first terminals connected to the third terminals of the first polarity separator and a pair of second terminals connected to the first terminals of the second polarity separator. The controlled barrier includes a polarity filter inductively coupled to the reversible memory cell and having a pair of first terminals connected to the third terminals of the circulator and a pair of second terminals connected to the complementary data outputs. In an illustrative embodiment, a circulating current in the reversible memory cell induces an oppositely circulating current in the polarity filter. In an illustrative embodiment, the reversible memory cell includes a first inductor having first and second terminals and a second inductor having first and second terminals. The reversible memory cell includes a first Josephson Junction having a first terminal coupled to the first terminal of the first inductor and a second terminal connected to the first terminal of the second inductor, and a second Josephson Junction having a first terminal coupled to the second terminal of the first inductor and a second terminal connected to the second terminal of the second terminal. In an illustrative embodiment, the polarity filter includes a first inductor having first and second terminals, a second inductor having first and second terminals, a third inductor having first and second terminals, a fourth inductor having first and second terminals, and a Josephson Junction having a first terminal coupled to the second terminal of the first inductor and connected to the first terminal of the second inductor and a second terminal connected to the second terminal of the third inductor and connected to the first terminal of the fourth inductor. BRIEF DESCRIPTIO