US-12620994-B2 - Fast calibration of phase lock loops

US12620994B2US 12620994 B2US12620994 B2US 12620994B2US-12620994-B2

Abstract

Phase lock loop calibration methods can be accelerated, and the accelerated method incorporated in integrated circuits and systems. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value.

Inventors

Kyungjin Kim
SHUNKEN HUANG
Ni Xu
ALEX NAZARI

Assignees

CREDO TECHNOLOGY GROUP LIMITED

Dates

Publication Date: 20260505
Application Date: 20240529

Claims (18)

1 . An integrated circuit that comprises: a phase lock loop configured to generate a clock signal, the phase lock loop having a calibration parameter that is adjustable over a predetermined range; and a controller configured to determine a calibrated value for the calibration parameter by: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value, wherein the controller is further configured to: determine a cycle count of the clock signal in a predetermined time; and measure the frequency error as an absolute value of a difference between the cycle count and a predetermined target count.
2 . The integrated circuit of claim 1 , wherein if the frequency error exceeds the predetermined threshold for the initial value of the calibration parameter the controller is configured to perform a bottom-up or top-down search to find the lower bound and the upper bound.
3 . The integrated circuit of claim 2 , wherein a step size for said stepping downward and said stepping upward is at least twice a step size of the bottom-up or top-down search.
4 . The integrated circuit of claim 1 , wherein the calibrated value is an integer closest to an average of the upper bound and the lower bound.
5 . The integrated circuit of claim 1 , wherein the initial value is the calibrated value determined during previous operation of the integrated circuit.
6 . The integrated circuit of claim 1 , wherein the phase lock loop is part of a first receiver having: a sampling element configured to sample a receive signal in accordance with a sampling clock; and a clock recovery circuit that derives the sampling clock from the clock signal.
7 . The integrated circuit of claim 6 , wherein the first receiver is one of multiple receivers in the integrated circuit, and wherein the controller is configured to use the calibrated value for the phase lock loop of the first receiver as an initial value of the calibration parameter for a phase lock loop of another one of the multiple receivers.
8 . The integrated circuit of claim 6 , further comprising a transmitter having a transmit phase lock loop with a transmit calibration parameter, wherein the controller is configured to use the calibrated value for the phase lock loop of the first receiver as an initial value of the transmit calibration parameter.
9 . The integrated circuit of claim 1 , wherein the phase lock loop includes a voltage-controlled oscillator with a variable capacitor, and wherein the calibration parameter is a baseline voltage of the variable capacitor.
10 . A calibration method for use in a controller configured to determine a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal, the method comprising: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value, wherein the frequency error is determined by: subtracting a cycle count of the clock signal in a predetermined time from a predetermined target count to obtain a difference; and taking an absolute value of the difference.
11 . The calibration method of claim 10 , wherein if the frequency error exceeds the predetermined threshold for the initial value of the calibration parameter the method further includes performing a bottom-up or top-down search to find the lower bound and the upper bound.
12 . The calibration method of claim 11 , wherein a step size for said stepping downward and said stepping upward is at least twice a step size of the bottom-up or top-down search.
13 . The calibration method of claim 10 , wherein the calibrated value is an integer closest to an average of the upper bound and the lower bound.
14 . The calibration method of claim 10 , wherein the initial value is the calibrated value determined during previous operation of the integrated circuit.
15 . The calibration method of claim 10 , wherein the phase lock loop is one of multiple phase lock loops in an integrated circuit, and wherein the initial value of the calibration parameter for one of the multiple phase lock loops is a calibrated value of the calibration parameter for another one of the multiple phase lock loops.
16 . The calibration method of claim 10 , wherein the phase lock loop includes a voltage-controlled oscillator with a variable capacitor, and wherein the calibration parameter is a baseline voltage of the variable capacitor.
17 . A non-transient information storage medium coupled to a controller to provide firmware that configures the controller to implement a calibration method to determine a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal, the calibration method comprising: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value, wherein if the frequency error exceeds the predetermined threshold for the initial value of the calibration parameter the calibration method further includes: performing a bottom-up or top-down search to find the lower bound and the upper bound, wherein a step size for said stepping downward and said stepping upward is at least twice a step size of the bottom-up or top-down search.
18 . The non-transient information storage medium of claim 17 , wherein the frequency error is determined by subtracting a cycle count of the clock signal in a predetermined time from a predetermined target count to obtain a difference and taking an absolute value of the difference.

Description

FIELD OF TECHNOLOGY The present invention relates generally to start-up processes for integrated circuits and, more particularly, to a technique for quickly calibrating one or more phase lock loops in an integrated circuit. BACKGROUND Digital communications occur between sending and receiving devices over an intermediate communications medium, or “channel” (e.g., a fiber optic cable, insulated copper wire, or a wireless connection). Each sending device typically transmits symbols at a fixed symbol rate, while each receiving device detects a (potentially corrupted) sequence of symbols and attempts to reconstruct the transmitted data. A “symbol” is a state or significant condition of the channel that persists for a fixed period, called a “symbol interval”. A symbol may be, for example, an electrical voltage or current level, an optical power level, a phase value, or a particular frequency or wavelength. A change from one channel state to another is called a symbol transition. Each symbol may represent (i.e., encode) one or more binary bits of the data. Alternatively, the data may be represented by symbol transitions, or by a sequence of two or more symbols. Many digital communication links use only one bit per symbol; a binary ‘0’ is represented by one symbol (e.g., an electrical voltage or current signal within a first range), and binary ‘1’ by another symbol (e.g., an electrical voltage or current signal within a second range), but higher-order signal constellations are known and frequently used. In 4-level pulse amplitude modulation (“PAM4”), each symbol interval may carry any one of four symbols, often denoted as −3, −1, +1, and +3. Two binary bits can thus be represented by each symbol. As part of the process for recovering digital data from the degraded analog signal, receivers obtain discrete samples of the signal. The sample timing is often a critical part of the process, as it directly affects the signal to noise ratio possessed by the discrete samples. Strategies for detecting and tracking optimal sample times exist with varying degrees of tradeoff between simplicity and performance, often relying on interpolation of a high frequency clock signal generated by a phase lock loop. For example, the Institute of Electrical and Electronics Engineers (IEEE) has published IEEE Std 802.3ba-2010, a standard which provides for Ethernet communications at rates as high as 100 Gb/s. The standard specifies multiple channels each having a symbol signaling rate as high as 25 Gb/s. Phase lock loops may be designed to derive a low-jitter 25 GHz clock signal from a more typical integrated circuit clock frequency of, e.g., 100 MHz. As with other integrated circuit designs, the chosen phase lock loop design must cope with potential changes in performance of its components due to process variation, supply voltage variation, and temperature variation (collectively, “PVT variations”) as well as drift due to component aging. The chosen design may accommodate one or more parameters that can be adjusted as part of a periodic calibration process to compensate for such changes. Such calibration is often part of the reset or power-on process of an integrated circuit. It should be noted that various components having phase lock loops (e.g., receivers, transmitters) may be unable to operate until suitable calibrated values are determined for adjustable parameters of the phase lock loops. Where a fast start-up is desired, it is desirable to ensure fast completion of the phase lock loop calibration process. SUMMARY Accordingly, there are disclosed herein fast calibration methods for phase lock loops as well as integrated circuits and systems that incorporate such methods. One illustrative calibration method for use in a controller determines a calibrated value of a calibration parameter for a phase lock loop configured to generate a clock signal. The method includes: finding a lower bound by stepping downward from an initial value of the calibration parameter while a frequency error remains below a predetermined threshold; finding an upper bound by stepping upward from the initial value while the frequency error remains below the predetermined threshold; and using a value greater than or equal to the lower bound and less than or equal to the upper bound as the calibrated value. One illustrative integrated circuit includes a phase lock loop and a controller configured to implement the above calibration method. The calibration method may illustratively be embodied on a non-transient information storage medium coupled to a controller to provide firmware that configures the controller to implement the calibration method. Each of the foregoing may be employed alone or in combination, together with any one or more of the following optional features in any suitable combination: 1. the controller is configured to determine a cycle count of the clock signal in a predetermined time. 2. the controller is configured to measure the frequency erro