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US-12620995-B2 - HD3 cancellation technique in RF DACs and digital transmitters

US12620995B2US 12620995 B2US12620995 B2US 12620995B2US-12620995-B2

Abstract

A transmitter includes a first circuit to generate multiphase pulses, and a second circuit to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses and to generate an output radiofrequency (RF) signal. The multiple pulses include multiple I pulses and multiple Q pulses each comprising a pulse that includes a duty cycle such that a first null appears at a third harmonic frequency in a frequency spectrum of the pulse.

Inventors

  • Mohyee Mikhemar
  • Alvin Lin Lai
  • Arya Behzad
  • Wei-Hong Chen
  • Ahmed Sayed Hamza

Assignees

  • AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Dates

Publication Date
20260505
Application Date
20230410

Claims (14)

  1. 1 . An apparatus, comprising: a first circuit configured to generate multiphase pulses; and a second circuit configured to mix a set of in-phase (I) data and quadrature (Q) data with the multiphase pulses, wherein: the multiphase pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle, wherein the first circuit is configured to generate the multiphase pulses having the duty cycle such that a first null appears at a third harmonic frequency of the pulse, and wherein the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55%.
  2. 2 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with the duty cycle within 30-35% such that the first null appears at the third harmonic frequency of the pulse to enable rejection of a third harmonic distortion (HD3).
  3. 3 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with the duty cycle within 45-55%.
  4. 4 . The apparatus of claim 3 , wherein the second circuit comprises a digital four-phase in-phase (I) and quadrature (Q) mixer and is configured to use the set of four-phase LO pulses.
  5. 5 . The apparatus of claim 1 , wherein the second circuit is further configured to mix the set of I-data and Q-data with the multiphase pulses to generate an output radio frequency (RF) signal.
  6. 6 . The apparatus of claim 1 , wherein the multiphase pulses comprise a set of four-phase LO pulses with a phase difference of 90 degrees.
  7. 7 . The apparatus of claim 6 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.
  8. 8 . An integrated circuit, comprising: a first circuit configured to generate a set of multiphase pulses with duty cycles; and a second circuit configured to receive the set of multiphase pulses and reject a third harmonic distortion (HD3) of the set of multiphase pulses, wherein the multiphase pulses comprise multiple in-phase (I) pulses and multiple quadrature (Q) pulses each comprising a pulse having a duty cycle, and the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the multiphase pulses to be within 30-35% or within 45-55% to reject the HD3.
  9. 9 . The integrated circuit of claim 8 , wherein: the set of multiphase pulses include a set of four-phase LO pulses, and wherein the second circuit comprises a mixer circuit configured to use the set of four-phase LO pulses to reject the HD3 and a third counter intermodulation (CIM3) of the set of multiphase pulses.
  10. 10 . The integrated circuit of claim 8 , wherein the set of multiphase pulses comprise a set of four-phase LO pulses with a phase difference of 90 degrees.
  11. 11 . The integrated circuit of claim 10 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.
  12. 12 . A communication device, comprising: a first circuit configured to generate a set of four-phase LO pulses; and a second circuit configured to mix in-phase (I) data and quadrature (Q) data with the set of four-phase LO pulses, wherein the first circuit is further configured to generate the set of four-phase LO pulses with duty cycles such that a first null of a frequency spectrum of a pulse of the set of four-phase LO pulses occurs at a third harmonic frequency, the four-phase LO pulses comprise multiple I pulses and multiple Q pulses each comprising a pulse having a duty cycle, and the first circuit comprises a delay locked loop (DLL) configured to selectively produce adjusted duty cycle values of the four-phase LO pulses to be within 30-35% or within 45-55%.
  13. 13 . The communication device of claim 12 , wherein the second circuit comprises a digital four-phase in-phase (I) and quadrature (Q) mixer circuit and is configured to use the set of four-phase LO pulses to improve a third harmonic distortion (HD3) and a third counter intermodulation (CIM3) of the pulse of the set of four-phase LO pulses.
  14. 14 . The communication device of claim 13 , wherein the set of four-phase LO pulses include a 0-degree-phase I pulse, a 90-degree-phase Q pulse, a 180-degree-phase I pulse, and a 270-degree-phase Q pulse.

Description

TECHNICAL FIELD The present description relates generally to radio frequency (RF) communications including, for example, third harmonic distortion (HD3) cancellation techniques in RF digital-to-analog converters (DACs) and digital transmitters. BACKGROUND Harmonic distortion (HD) is common in electronic circuits such as amplifiers, modulators, and other circuits due to a non-ideal transfer function such as nonlinearity. This can cause a portion of the output-signal power to appear at frequencies which are multiples of the frequency of the input signal. For example, the HD3 is the distortion due to output-signal components appearing at three times the frequency of the input signal. Additionally, distortion that can happen during modulation of a signal is a third counter intermodulation (CIM3), which creates a product that lands at three times the signal frequency (3fsig) on the other side of the local oscillator (LO) frequency (fLO), that is at a frequency of fLO-3fsig. Existing techniques for countering HD3 and CIM3 include using 8-phase clocking or applying inductor-capacitor (LC) filters tuned at a frequency of 3fLO. These techniques, although may work for their intended purposes, have shortcomings such as high-power consumption and large chip area (due to large inductors). BRIEF DESCRIPTION OF THE DRAWINGS Certain features of the subject technology are set forth in the appended claims. However, for purposes of explanation, several aspects of the subject technology are depicted in the following figures. FIG. 1 is a high-level block diagram illustrating an example of a digital transmitter within which some aspects of the subject technology are implemented. FIGS. 2A, 2B, and 2C are a schematic diagram illustrating an example of a delay locked loop (DLL) providing clock signals for a digital transmitter (DTX) and corresponding charts depicting clock signals, according to aspects of the subject technology. FIGS. 3A, 3B, 3C, and 3D illustrate a schematic diagram of an example implementation of in-phase (I) and quadrature (Q) mixer and examples of input, output, and four-phase pulses. FIGS. 4A, 4B, and 4C are charts illustrating an example LO pulse and the corresponding frequency spectrum and a duty cycle table. FIG. 5 is a chart illustrating an example of an output frequency spectrum associated with using four-phase clock pules with 33% duty cycle. FIG. 6 is a flow diagram illustrating an example of a process for cancelling HD3 and CMI3, according to aspects of the subject technology. FIG. 7 illustrates an example of a wireless communication device within which some aspects of the subject technology are implemented. DETAILED DESCRIPTION The detailed description set forth below is intended as a description of various configurations of the subject technology and is not intended to represent the only configurations in which the subject technology may be practiced. The appended drawings are incorporated herein and constitute a part of the detailed description. The detailed description includes specific details for the purpose of providing a thorough understanding of the subject technology. However, the subject technology is not limited to the specific details set forth herein and may be practiced using one or more implementations. In one or more instances, structures and components are shown in block-diagram form in order to avoid obscuring the concepts of the subject technology. According to some aspects, the subject technology is directed to an HD3 cancellation technique in RF DACs and digital transmitters. The HD3 cancellation technique of the subject technology uses multiphase clock pulses with a duty cycle adjusted to produce a zero at the third harmonic frequency in a corresponding frequency spectrum of the clock pulse. In some embodiments, the duty cycle of a clock pulse is a ratio of the clock pulse width to a period (inverse of frequency) of the clock pulse. For example, a clock pulse with a frequency of 1 KHz (1 mS period) and a pulse width of 500 μS has a duty cycle of 50% (0.5/1=0.50) In one or more embodiments, the multiphase clock pulses include a set of four-phase clock pulses. In some embodiments, the duty cycle of the four-phase clock pulses can be 33% or 50%. In some aspects, when boosting the output power of the digital transmitter can be achieved without a high level of CIM3 rejection, the four-phase clock pulses with 50% duty cycle can be used to cancel HD3. The disclosed cancellation technique can achieve about 20 decibels (dB) rejection of the HD3 and CIM3, similar to the existing techniques that use LC filters tuned at 3 fLO. However, the disclosed technique is implemented with a considerably smaller footprint because it does not need large inductors as used in the LC filters. Furthermore, the disclosed cancellation technique consumes about 10-50% lower power as compared to the existing 8-phase clocking technique. FIG. 1 is a high-level block diagram illustrating an example of a digital tra