US-12620996-B2 - Signal processor with A-D converter and reservoir unit

US12620996B2US 12620996 B2US12620996 B2US 12620996B2US-12620996-B2

Abstract

A signal processor includes an input unit, an analog-digital converter, and a reservoir unit. The input unit receives an input of a first analog signal. The analog-digital converter converts the first analog signal to a first digital signal. The reservoir unit receives an input of at least a part of the first digital signal. The reservoir unit determines a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output.

Inventors

Yukio Terasaki

Assignees

TDK CORPORATION

Dates

Publication Date: 20260505
Application Date: 20230831

Claims (19)

1 . A signal processor comprising: an input unit configured to receive an input of a first analog signal; an analog-digital converter configured to convert the first analog signal to a first digital signal; and a reservoir unit configured to receive an input of at least a part of the first digital signal, wherein the analog-digital converter is connected to each of the input unit and the reservoir unit and receives and converts the first digital signal from the input unit, and wherein the reservoir unit determines by learning a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output wherein the control signal is input to the analog-digital converter, and wherein the analog-digital converter changes a sampling timing at which the first analog signal is converted to the first digital signal at a timing at which the control signal is input.
2 . The signal processor according to claim 1 , wherein a second analog signal is additionally input to the input unit.
3 . The signal processor according to claim 2 , further comprising a second analog-digital converter configured to receive an input of the second analog signal.
4 . The signal processor according to claim 1 , wherein the reservoir unit acquires the rule of the timing at which the control signal is output through learning under the condition that a rate of correct answers of the reservoir unit increases in a learning process.
5 . The signal processor according to claim 1 , wherein the reservoir unit performs reinforcement learning.
6 . The signal processor according to claim 1 , wherein the reservoir unit outputs an output target value of the reservoir unit and a likelihood of an actual output from the reservoir unit and the control signal decreases a sampling rate in the period while the likelihood is low.
7 . The signal processor according to claim 1 , wherein the reservoir unit is a state machine by logical circuits.
8 . The signal processor according to claim 1 , wherein the reservoir unit is a physical reservoir including elements or circuits.
9 . The signal processor according to claim 1 , wherein the reservoir unit includes a first unit and a second unit, wherein the first unit outputs an estimated solution to a task, and wherein the second unit determines the rule of a timing at which the control signal is output.
10 . A signal processor comprising: an input unit configured to receive an input of a first analog signal; an analog-digital converter configured to convert the first analog signal to a first digital signal; and a reservoir unit configured to receive an input of at least a part of the first digital signal, wherein the analog-digital converter is connected to each of the input unit and the reservoir unite and receives and converts the first digital signal from the input unit, wherein the reservoir unit determines by learning a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output, wherein the control signal is input to the analog-digital converter, and wherein the analog-digital converter extracts a part of the first digital signal.
11 . The signal processor according to claim 10 , wherein a second analog signal is additionally input to the input unit.
12 . The signal processor according to claim 11 , further comprising a second analog-digital converter configured to receive an input of the second analog signal.
13 . The signal processor according to claim 10 , wherein the reservoir unit acquires the rule of the timing at which the control signal is output through learning under the condition that a rate of correct answers of the reservoir unit increases in a learning process.
14 . The signal processor according to claim 10 , wherein the reservoir unit performs reinforcement learning.
15 . The signal processor according to claim 10 , wherein the reservoir unit outputs an output target value of the reservoir unit and a likelihood of an actual output from the reservoir unit and the control signal decreases a sampling rate in the period while the likelihood is low.
16 . The signal processor according to claim 10 , wherein the reservoir unit is a state machine by logical circuits.
17 . The signal processor according to claim 10 , wherein the reservoir unit is a physical reservoir including elements or circuits.
18 . The signal processor according to claim 10 , wherein the reservoir unit includes a first unit and a second unit, wherein the first unit outputs an estimated solution to a task, and wherein the second unit determines the rule of a timing at which the control signal is output.
19 . A signal processor comprising: an input unit configured to receive an input of a first analog signal; an analog-digital converter configured to convert the first analog signal to a first digital signal; and a reservoir unit configured to receive an input of at least a part of the first digital signal, wherein the analog-digital converter is connected to each of the input unit and the reservoir unite and receives and converts the first digital signal from the input unit, wherein the reservoir unit determines by learning a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output, and wherein the number of signals input to the reservoir unit in a predetermined period in response to the control signal is equal to or less than short-term memory property of the reservoir unit.

Description

TECHNICAL FIELD The present invention relates to a signal processor. BACKGROUND ART A neuromorphic device is a device that imitates the human brain using a neural network. A neuromorphic device artificially imitates a relationship between neurons and synapses in the human brain. For example, a neuromorphic device includes nodes that are hierarchically arranged (neurons in the brain) and transmission means that connect the nodes (synapses in the brain). A neuromorphic device enhances a rate of correct answers to questions by training the transmission means (synapses). Learning is finding knowledge from information which is likely to be used in the future, and a neuromorphic device weights data that it receives. A recurrent neural network is known as one of the neural network. A recurrent neural network can handle nonlinear time-series data. Nonlinear time-series data is the data whose value changes with the elapse of time, and stock prices is one of such examples. A recurrent neural network can process time-series data by feeding processing results of neurons in a subsequent stage back to neurons in a preceding stage. Reservoir computing is a means for realizing a recurrent neural network. Reservoir computing performs a recursive processing by having signals to interact based on the internal coupling. Reservoir computing is performed by a reservoir computer device. Short-term memory property is one of the performance metrics required for a reservoir computer device. Short-term memory property is a criterion for determining how past information can be stored or forgotten. In general, a reservoir computer device having short-term memory property optimal for a given task, outputs an estimated solution by considering data in a required section up to the current time from time-series data and ignoring unnecessary past data older before. For example, a reservoir computer device with excellent short-term memory property outputs an estimated solution with consideration of past data in time-series data, but a reservoir computer device with poor short-term memory property outputs an estimated solution using most recent data in time-series data. For example, it is described in Patent Document 1 that a first reservoir taking charge of short-term memory and a second reservoir taking charge of nonlinear processing are used to enhance short-term memory property of a reservoir computer device. CITATION LIST Patent Document [Patent Document 1]PCT International Publication No. WO2022/024167 SUMMARY OF INVENTION Technical Problem Short-term memory property and nonlinear transformation performance are known as significant aspects of performance required for a reservoir computer device, but short-term memory property and nonlinear transformation performance of the reservoir computer device have a trade-off relationship and thus it is difficult to satisfy both. Accordingly, there is a need for a new method satisfying both properties. The present invention was made in consideration of the aforementioned circumstances and provides a signal processor for realizing a reservoir computer device having the equivalent performance as a reservoir computer device with excellent short-term memory property. Solution to Problem (1) A signal processor according to a first aspect includes an input unit, an analog-digital converter, and a reservoir unit. The input unit receives an input of a first analog signal. The analog-digital converter converts the first analog signal to a first digital signal. The reservoir unit receives an input of at least a part of the first digital signal. The reservoir unit determines a rule of a timing at which a control signal for extracting a part of the first analog signal or the first digital signal is output.(2) In the signal processor according to the aspect, the control signal may be input to the analog-digital converter. The analog-digital converter may change a sampling timing at which the first analog signal is converted to the first digital signal at a timing at which the control signal is input.(3) In the signal processor according to the aspect, the control signal may be input to the analog-digital converter. The analog-digital converter may extract a part of the first digital signal.(4) In the signal processor according to the aspect, the number of signals input to the reservoir unit in a predetermined period in response to the control signal may be equal to or less than short-term memory property of the reservoir unit.(5) In the signal processor according to the aspect, a second analog signal may be additionally input to the input unit.(6) The signal processor according to the aspect may further include a second analog-digital converter configured to receive an input of the second analog signal.(7) In the signal processor according to the aspect, the reservoir unit may acquire the rule of the timing at which the control signal is output through learning under the condition that a rate of correct answers