US-12620997-B2 - High speed monobit analog-digital converter system with integrated programmable front-end

US12620997B2US 12620997 B2US12620997 B2US 12620997B2US-12620997-B2

Abstract

A monobit analog-digital converter (ADC) system and method are disclosed, the system comprising a front-end signal conditioning system equipped with a programmable attenuator and amplifier for processing analog signals, where the attenuator, which may include a cascade of programmable attenuator cells, is controlled by an attenuation control signal to adjust signal attenuation to cause a signal-to-noise ratio (SNR) in the negative domain, after which an amplifier amplifies the attenuated signal with the suitable SNR, where the amplified signal is then converted to a monobit signal by a monobit ADC, thereby achieving an ADC system that enables conditioning and digitizing of RF signals over a wide range of input signal powers with control over the output spectrum signal power and harmonics to achieve low-power real-time general-purpose broadband blocker detection for adaptive radios and for interference detection, main beam radar signal detection, and instantaneous frequency measurement, among other fields requiring general-purpose blocker identification with low size, weight, power, and cost (SWaP-C).

Inventors

Renyuan Wang
Cameron Huang
Steven E. Turner
Jeffrey F. Bonner-Stewart

Assignees

BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Dates

Publication Date: 20260505
Application Date: 20240422

Claims (15)

1 . An analog-digital converter system comprising: a front-end signal conditioning system comprising an attenuator configured to attenuate an analog signal and an amplifier in operative communication with the attenuator, the amplifier configured to amplify the analog signal after attenuation by the attenuator; and a monobit analog-digital converter in operative communication with the amplifier, the monobit analog-digital converter configured to convert the analog signal to a monobit signal, wherein the attenuation of the attenuator and the amplification of the amplifier are set so as to reduce the signal-to-noise ratio into the negative SNR domain, and so that the signal levels of the analog signal will be within the dynamic range of the monobit analog-digital converter; and wherein the attenuator comprises a plurality of cascade-connected attenuator cells.
2 . The analog-digital converter system of claim 1 , wherein attenuation of the attenuator is programmable.
3 . The analog-digital converter system of claim 1 , wherein the attenuator is configured to be programmable by bypassing individual attenuator cells in response to an attenuation control signal.
4 . The analog-digital converter system of claim 1 , wherein gain of the amplifier is programmable.
5 . The analog-digital converter system of claim 1 , wherein the monobit analog-digital converter comprises: an interleaved sampler configured for interleaved sampling of the output of the monobit analog-digital converter to produce a plurality of data streams; and a demultiplexer configured to further separate the plurality of data streams into a greater plurality of data streams.
6 . The analog-digital converter system of claim 1 , further comprising a fast Fourier transformer in operative communication with the monobit analog-digital converter, wherein the fast Fourier transformer is configured to perform fast Fourier transformation on an output of the monobit analog-digital converter.
7 . An analog-digital converting method, comprising: attenuating an input signal using an attenuator; using an amplifier to amplify the output signal from the attenuator; tuning the attenuator, wherein tuning of the attenuator is achieved by bypassing an attenuator cell in an attenuator that comprises a plurality of attenuator cells; and using a monobit analog-digital convertor to perform monobit analog-digital conversion, wherein the attenuation of the attenuator and the amplification of the amplifier are set so as to reduce the signal-to-noise ratio into the negative SNR domain, and so that the signal levels of the analog signal will be within the dynamic range of the monobit analog-digital converter.
8 . The method of claim 7 , further comprising tuning the amplifier.
9 . The method of claim 7 , further comprising sampling a plurality of monobit analog-digital convertor outputs and demultiplexing the sampled results.
10 . The method of claim 7 , further comprising performing digital post-processing on an output of the monobit analog-digital convertor.
11 . The method of claim 10 , wherein the digital post-processing on an output of the monobit analog-digital convertor is performance of a fast Fourier transform.
12 . The method of claim 10 , wherein a result of the digital post-processing is used to adjust the attenuation of the attenuator and/or adjust the amplification of the amplifier.
13 . The method of claim 10 , wherein a result of the digital post-processing is used to adjust attenuation of a band-stop filter that is configured to attenuate a frequency band of the input signal.
14 . A receiver comprising: an analog-digital converter system that comprises: a front-end signal conditioning system comprising an attenuator configured to attenuate an analog signal and an amplifier in operative communication with the attenuator, the amplifier configured to amplify the analog signal after attenuation by the attenuator; and a monobit analog-digital converter in operative communication with the amplifier, the monobit analog-digital converter configured to convert the analog signal to a monobit signal; post-processing circuitry configured to perform digital post-processing on said monobit signal; and a band-stop filter to attenuate one or more blocking frequency identified through said digital post-processing wherein the attenuation of the attenuator and the amplification of the amplifier are set so as to reduce the signal-to-noise ratio into the negative SNR domain, and so that the signal levels of the analog signal will be within the dynamic range of the monobit analog-digital converter.
15 . The receiver of claim 14 , wherein the attenuation of the attenuator is programmable.

Description

STATEMENT OF GOVERNMENT INTEREST This invention was made with government support under Contract No. FA8650-21-C-7001 awarded by DARPA MTO. The United States Government has certain rights in this invention. FIELD OF THE DISCLOSURE The following disclosure relates generally to interference (i.e., blocker) identification, and, more specifically, to utilizing high speed monobit analog-to-digital converters (ADCs) with integrated programmable front ends for low-power, low system overhead broadband applications. BACKGROUND Adaptive radios, used in various applications, now extend beyond the Ku band (12-18 GHZ). In congested electromagnetic environments, blockers (jammers) can saturate receivers and impair system functionality. Broadband real-time interference detection is crucial for achieving blocker rejection, requiring knowledge of frequencies, power levels, bandwidths, and possibly waveforms. Efficient detection with low latency and minimal system impact in terms of size, power, cost, and complexity is desired. Use of the main receiver for interference detection diverts resources, so alternative methods like dispersive frequency-to-time mapping detection and other auxiliary receivers have been proposed; however these approaches have limitations in terms of instantaneous bandwidth, frequency resolution, latency, dynamic range and SWaP (size, weight, and power). Monobit ADCs offer simplicity and lower power consumption, but face dynamic range limitations. A solution is sought for wideband, general-purpose blocker identification with low size, weight, power, and cost (SWaP-C). SUMMARY The present disclosure teaches a high-speed monobit ADC system with a programmable, on-chip RF front-end. Embodiments are capable of directly sampling from 2 GHz to 20 GHz for broadband, general purpose blocker detection. One embodiment of the present invention provides an analog-digital converter system comprising: a front-end signal conditioning system comprising an attenuator configured to attenuate an analog signal and an amplifier in operative communication with the attenuator, the amplifier configured to amplify the analog signal after attenuation by the attenuator; and a monobit analog-digital converter in operative communication with the amplifier, the monobit analog-digital converter configured to convert the analog signal to a monobit signal, wherein the attenuation of the attenuator and the amplification of the amplifier are set so as to reduce the signal-to-noise ratio into the negative SNR domain, and so that the signal levels of the analog signal will be within the dynamic range of the monobit analog-digital converter. Another embodiment of the present invention provides such an analog-digital converter system, wherein attenuation of the attenuator is programmable. A further embodiment of the present invention provides such an analog-digital converter system, wherein the attenuator comprises a plurality of cascade-connected attenuator cells. Yet another embodiment of the present invention provides such an analog-digital converter system, wherein the attenuator is configured to be programmable by bypassing individual attenuator cells in response to an attenuation control signal. A yet further embodiment of the present invention provides such an analog-digital converter system, wherein gain of the amplifier is programmable. Still another embodiment of the present invention provides such an analog-digital converter system, wherein the monobit analog-digital converter comprises: an interleaved sampler configured for interleaved sampling of the output of the monobit analog-digital converter to produce a plurality of data streams; and a demultiplexer configured to further separate the plurality of data streams into a greater plurality of data streams. A still further embodiment of the present invention provides such an analog-digital converter system, further comprising a fast Fourier transformer in operative communication with the monobit analog-digital converter, wherein the fast Fourier transformer is configured to perform fast Fourier transformation on an output of the monobit analog-digital converter. Even another embodiment of the present invention provides an analog-digital converting method, comprising: attenuating an input signal using an attenuator; using an amplifier to amplify the output signal from the attenuator; and using a monobit analog-digital convertor to perform monobit analog-digital conversion, wherein the attenuation of the attenuator and the amplification of the amplifier are set so as to reduce the signal-to-noise ratio into the negative SNR domain, and so that the signal levels of the analog signal will be within the dynamic range of the monobit analog-digital converter. An even further embodiment of the present invention provides such a method, further comprising tuning the attenuator. A still even another embodiment of the present invention provides such a method, wherein tuning of the attenuator