US-12620999-B2 - Conversion start-up of an analog-to-digital converter within an integrated circuit

Abstract

An analog-to-digital converter is clocked by a converter clock signal. A first clock signal has a frequency multiple of the frequency of the converter clock signal. A timer, which is clocked with the rhythm of the first clock signal, has a timing period multiple of the period of the converter clock signal. A processor is configured to control the converter based on the timing signal delivered by the timer, and has a first operating mode in which it is further configured to clock the timer synchronously with the converter clock signal and to deliver based on the timing signal, a periodic first conversion control signal of the converter, having a period multiple of the period of the converter clock signal and a constant first phase difference with the converter clock signal.

Inventors

• Sandrine Ollivry
• Jean-Francois Link

Assignees

• STMICROELECTRONICS INTERNATIONAL N.V.

Dates

Publication Date

20260505

Application Date

20240613

Priority Date

20230623

Claims (20)

1. 1 . An integrated circuit, comprising: at least one first analog-to-digital converter, of the integrated circuit, configured to be clocked by a converter clock signal having a first frequency and a first period; a clock input, of the integrated circuit, configured to receive a first clock signal having a second frequency multiple of the first frequency of the converter clock signal; a timer, of the integrated circuit, configured to clock with a rhythm of the first clock signal and having a second period multiple of the first period of the converter clock signal; and a processor, of the integrated circuit, configured to control the at least one first analog-to-digital converter based on a timing signal delivered by the timer, wherein the processor has a first operating mode in which the processor is further configured to clock the timer synchronously with the converter clock signal, and to deliver, based on the timing signal, a first periodic conversion control signal to the at least one first analog-to-digital converter, the first periodic conversion control signal having a third period multiple of the first period of the converter clock signal and a first constant phase difference with the converter clock signal.
2. 2 . The integrated circuit according to claim 1 , wherein: the integrated circuit further comprises a control input configured to receive a conversion control external signal; the processor is configured, in the first operating mode, in response to the conversion control external signal, to generate an edge of the periodic first conversion control signal each time the timer reaches a selected timing value; and the at least one first analog-to-digital converter is configured to periodically start conversions after a fixed and constant first period after the edge of the periodic first conversion control signal.
3. 3 . The integrated circuit according to claim 2 , wherein the processor is further configured to deliver the converter clock signal and a sync signal indicating a first time point of each period of the converter clock signal, wherein the first time point is identical for each period, and, in a presence of the conversion control external signal, to delay triggering of the timer until a next first time point.
4. 4 . The integrated circuit according to claim 2 , wherein the processor is configured to select the selected timing value from among several predefined timing values.
5. 5 . The integrated circuit according to claim 2 , wherein the timer is reset synchronously with the converter clock signal.
6. 6 . The integrated circuit according to claim 1 , further comprising at least one second analog-to-digital converter that is clocked by the converter clock signal, and the processor is further configured, in the first operating mode, to deliver a second periodic conversion control signal having a fourth period multiple of the first period of the converter clock signal and a second constant phase difference with the converter clock signal.
7. 7 . The integrated circuit according to claim 1 , wherein the processor has a second operating mode in which the processor is configured to clock the timer asynchronously with the converter clock signal.
8. 8 . The integrated circuit according to claim 7 , further comprising a selection input configured to receive a selection signal, wherein the first and second operating modes of the processor are selectable by the selection signal.
9. 9 . A microcontroller, comprising: at least one first analog-to-digital converter configured to be clocked by a converter clock signal having a first frequency and a first period; a clock input configured to receive a first clock signal having a second frequency multiple of the first frequency of the converter clock signal; a timer configured to clock with a rhythm of the first clock signal and having a second period multiple of the first period of the converter clock signal; and a processor configured to control the at least one first analog-to-digital converter based on a timing signal delivered by the timer, wherein the processor has a first operating mode in which the processor is further configured to clock the timer synchronously with the converter clock signal, and to deliver, based on the timing signal, a first periodic conversion control signal to the at least one first analog-to-digital converter, the first periodic conversion control signal having a third period multiple of the first period of the converter clock signal and a first constant phase difference with the converter clock signal.
10. 10 . The microcontroller according to claim 9 , wherein: the microcontroller further comprises a control input configured to receive a conversion control external signal; the processor is configured, in the first operating mode, in response to the conversion control external signal, to generate an edge of the periodic first conversion control signal each time the timer reaches a selected timing value; and the at least one first analog-to-digital converter is configured to periodically start conversions after a fixed and constant first period after the edge of the periodic first conversion control signal.
11. 11 . The microcontroller according to claim 9 , further comprising at least one second analog-to-digital converter that is clocked by the converter clock signal, and the processor is further configured, in the first operating mode, to deliver a second periodic conversion control signal having a fourth period multiple of the first period of the converter clock signal and a second constant phase difference with the converter clock signal.
12. 12 . The microcontroller according to claim 9 , wherein the processor has a second operating mode in which the processor is configured to clock the timer asynchronously with the converter clock signal.
13. 13 . A method of operating an integrated circuit, the method comprising: clocking, by a converter clock signal having a first frequency and a first period, at least one first analog-to-digital converter; receiving, by a clock input, a first clock signal having a second frequency multiple of the first frequency of the converter clock signal; clocking a timer with a rhythm of the first clock signal and with a second period multiple of the first period of the converter clock signal; controlling, by a processor, the at least one first analog-to-digital converter based on a timing signal delivered by the timer; operating, by the processor, in a first operating mode comprising: clocking, by the processor, the timer synchronously with the converter clock signal; and delivering, by the processor, based on the timing signal, a first periodic conversion control signal to the at least one first analog-to-digital converter, the first periodic conversion control signal having a third period multiple of the first period of the converter clock signal and a first constant phase difference with the converter clock signal.
14. 14 . The method according to claim 13 , wherein: receiving, by a control input of the integrated circuit, a conversion control external signal; generating, by the processor in the first operating mode, in response to the conversion control external signal, an edge of the periodic first conversion control signal each time the timer reaches a selected timing value; and periodically starting, by the at least one first analog-to-digital converter, conversions after a fixed and constant first period after the edge of the periodic first conversion control signal.
15. 15 . The method according to claim 14 , further comprising, by the processor: delivering the converter clock signal and a sync signal indicating a first time point of each period of the converter clock signal, the first time point being identical for each period; and delaying, in a presence of the conversion control external signal, triggering of the timer until a next first time point.
16. 16 . The method according to claim 14 , further comprising, by the processor, selecting the selected timing value from among several predefined timing values.
17. 17 . The method according to claim 14 , further comprising resetting the timer synchronously with the converter clock signal.
18. 18 . The method according to claim 13 , further comprising: clocking, by the converter clock signal, at least one second analog-to-digital converter; and delivering, by the processor, in the first operating mode, a second periodic conversion control signal having a fourth period multiple of the first period of the converter clock signal and a second constant phase difference with the converter clock signal.
19. 19 . The method according to claim 13 , further comprising, by the processor, in a second operating mode, clocking the timer asynchronously with the converter clock signal.
20. 20 . The method according to claim 19 , further comprising receiving, by a selection input, a selection signal, the first and second operating modes of the processor being selectable by the selection signal.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application claims the benefit of French Patent Application No. 2306551, filed on Jun. 23, 2023, which application is hereby incorporated herein by reference. TECHNICAL FIELD Embodiments relate to integrated circuits, in particular microcontrollers, for example those embedding one or more analog-to-digital converters as well as a timer, and associated methods, and more particularly to management of the start-up of the conversion periods of the converter(s). BACKGROUND Some current microcontrollers offer a so-called “fixed trigger latency” feature, i.e., a fixed duration or latency between the time of commanding or triggering an analog-to-digital conversion and the time when this conversion actually starts. Such a feature is useful in particular in motor control or audio processing applications. The timer then drives the application based on a pulse-width modulated signal (“PWM: Pulse Width Modulation”). Analog-to-digital conversions are regularly controlled at each period of the PWM signal and for some applications it is essential that the aforementioned latency does not change from one period to another, i.e., that there is no jitter. This is ensured by construction when the converter and the timer are respectively clocked by synchronous clocks. It is possible to obtain a fixed latency when the converter and the timer are respectively clocked by pseudo-synchronous clocks with low frequency ratios (2 or 4) but at the expense of an alteration of the performances of the converter. Yet, the maximum clock frequency of an analog-to-digital converter is currently in the range of 75 MHz whereas that of a timer could range up to several hundred MHz. Therefore, the triggering signal of a conversion, emitted by the timer, could occur at any time over the period of the clock signal clocking the converter. Consequently, the latency between the triggering time point and the actual conversion start time point could change. Hence, there is a need to offer a fixed latency between the time point of triggering and the time point of actual starting of the conversion, even for high frequency ratios between the clock frequency of the timer and the clock frequency of the converter, and that being so without alteration of the performances of the converter. SUMMARY According to one aspect, an integrated circuit, for example a microcontroller, is provided, comprising: at least one first analog-to-digital converter which can be clocked by a converter clock signala clock input for receiving a first clock signal having a frequency multiple of the frequency of the converter clock signal,a timer, which can be clocked with the rhythm of the first clock signal and having a timing period multiple of the period of the converter clock signal, anda processor configured to control the at least one first converter based on the timing signal delivered by the timer. The processor has a first operating mode in which it is further configured to clock the timer synchronously with the converter clock signal and to deliver based on the timing signal delivered by the timer, a periodic first conversion control signal of the converter, having a period multiple of the period of the converter clock signal and a constant first phase difference with the converter clock signal. Hence, a fixed (constant) and predictable latency is obtained between the triggering time point and the actual conversion start time point, even for high frequency ratios between the clock frequency of the timer and the clock frequency of the converter. According to one embodiment, the integrated circuit further comprises a control input for receiving a conversion control external signal, for example a bit. In the first operating mode, in response to the conversion control external signal, the processor is configured to: generate an edge, for example a rising edge, of the periodic first conversion control signal, each time the timer reaches a selected timing value, for example yet not necessarily the value corresponding to the value of the timing period. The first converter is configured to periodically begin conversions after a fixed and constant first duration after the edge of the periodic first conversion control signal. This fixed duration may be equal to an integer number of periods of the converter clock signal. It may also be equal to a period fraction of the converter clock signal or be equal to x cycles or periods of the first clock signal increased by y cycles or periods of the converter clock signal. Advantageously, the processor is further configured to deliver the converter clock signal as well as a sync signal indicating a first time point, for example yet not necessarily the beginning, of each period of the converter clock signal, the first time point being identical for each period, and, in the presence of the conversion control external signal, to delay triggering of the timer until the next first time point, for example th