US-12621000-B2 - Successive approximation register analog-to-digital converter and operating method thereof

US12621000B2US 12621000 B2US12621000 B2US 12621000B2US-12621000-B2

Abstract

The present disclosure provides an analog-to-digital converter including a comparator, a first capacitor array, a second capacitor array and a controller. The first capacitor array is controlled by a first control signal of the controller and coupled to a first input terminal of the comparator. The second capacitor array is controlled by a second control signal of the controller and coupled to a second input terminal of the comparator. The equivalent capacitance of a most significant bit (MSB) of the first and second capacitor arrays is two times of that of (MSB-1). The MSB includes multiple capacitors and the (MSB-1) includes at least one capacitor. The capacitance of each capacitor of the MSB is identical to that of each capacitor of the (MSB-1).

Inventors

Shiue-Shin Liu
Hou-Tse YU

Assignees

PIXART IMAGING INC.

Dates

Publication Date: 20260505
Application Date: 20240514

Claims (20)

1 . An analog-to-digital converter, comprising: a comparator, comprising a non-inverting input terminal and an inverting input terminal; a first capacitor array, coupled to the non-inverting input terminal of the comparator, and comprising a first most significant bit (MSB) and a first (MSB-1), wherein the first MSB includes multiple capacitors, the first (MSB-1) includes at least one capacitor, and capacitance of each of the multiple capacitors of the first MSB is identical to that of each of the at least one capacitor of the first (MSB-1); and multiple first switches, each respectively coupled to a first end of a corresponding capacitor of the first capacitor array, wherein switches among the multiple first switches and coupled to the capacitors of the first MSB and the first (MSB-1) are switched only according to whether a first analog input inputted into the non-inverting input terminal is larger than or smaller than and a second analog input inputted into the inverting input terminal, and switches among the multiple first switches and coupled to capacitors other than the capacitors of the first MSB and the first (MSB-1) are switched according to a fast binary window operation.
2 . The analog-to-digital converter as claimed in claim 1 , further comprising: a controller, configured to output a first control signal to control a line to be coupled to the multiple first switches.
3 . The analog-to-digital converter as claimed in claim 2 , further comprising: a first ground line; a first reference line; and a first common line, wherein the first ground line, the first reference line and the first common line are selectively coupled to the first end of each capacitor of the first capacitor array via a corresponding first switch among the multiple first switches.
4 . The analog-to-digital converter as claimed in claim 3 , further comprising a first sampling switch coupled to a second end of each capacitor of the first capacitor array.
5 . The analog-to-digital converter as claimed in claim 2 , further comprising: a second capacitor array, coupled to the inverting input terminal of the comparator, and comprising a second MSB and a second (MSB-1), wherein the second MSB includes multiple capacitors, the second (MSB-1) includes at least one capacitor, and capacitance of each of the multiple capacitors of the second MSB is identical to that of each of the at least one capacitor of the second (MSB-1).
6 . The analog-to-digital converter as claimed in claim 5 , further comprising: multiple second switches, each respectively coupled to a first end of a corresponding capacitor of the second capacitor array, wherein the controller is further configured to output a second control signal to control a line coupled to the multiple second switches.
7 . The analog-to-digital converter as claimed in claim 6 , further comprising: a second ground line; a second reference line; and a second common line, wherein the second ground line, the second reference line and the second common line are selectively coupled to the first end of each capacitor of the second capacitor array via a corresponding second switch among the multiple second switches.
8 . The analog-to-digital converter as claimed in claim 7 , further comprising a second sampling switch coupled to a second end of each capacitor of the second capacitor array.
9 . The analog-to-digital converter as claimed in claim 1 , wherein the first MSB includes two capacitors, and the two capacitors are coupled in parallel and have the identical capacitance, the first (MSB-1) includes one capacitor, and capacitance of a (MSB-2) of the first capacitor array is ½ of that of the one capacitor of the first (MSB-1).
10 . The analog-to-digital converter as claimed in claim 1 , wherein the first MSB includes four capacitors, and the four capacitors are coupled in parallel and have the identical capacitance, the first (MSB-1) includes two capacitors, and the two capacitors are coupled in parallel and have the identical capacitance, and capacitance of a (MSB-2) of the first capacitor array is identical to that of each of the two capacitors of the first (MSB-1).
11 . An operating method of an analog-to-digital converter, the analog-to-digital converter comprising a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator, a most significant bit (MSB) of each of the first capacitor array and the second capacitor array including two capacitors, and a (MSB-1) of each of the first capacitor array and the second capacitor array including one capacitor, the operating method comprising: coupling the two capacitors of the MSB and the one capacitor of the (MSB-1) of each of the first and second capacitor arrays to a common voltage; grounding the two capacitors of the MSB of the first capacitor array upon a first analog input inputted into the non-inverting input terminal being larger than a second analog input inputted into the inverting input terminal; coupling the two capacitors of the MSB of the first capacitor array to a reference voltage upon the first analog input being smaller than the second analog input, wherein the reference voltage is 2 times of the common voltage; and controlling switches, coupled to capacitors among the first capacitor array and the second capacitor array but not coupled to the MSB and the (MSB-1) of the first and second capacitor arrays, according to a fast binary window operation.
12 . The operating method as claimed in claim 11 , further comprising: coupling the two capacitors of the MSB of the second capacitor array to the reference voltage upon the two capacitors of the MSB of the first capacitor array being grounded; and grounding the two capacitors of the MSB of the second capacitor array upon the two capacitors of the MSB of the first capacitor array being coupled to the reference voltage.
13 . The operating method as claimed in claim 11 , wherein after the two capacitors of the MSB of the first capacitor array are grounded, the operating method further comprises: grounding the one capacitor of the (MSB-1) of the first capacitor array upon the first analog input being larger than the second analog input; and switching back one of the two capacitors of the MSB of the first capacitor array to the common voltage upon the first analog input being smaller than the second analog input.
14 . The operating method as claimed in claim 13 , wherein after the one capacitor of the (MSB-1) of the first capacitor array is grounded, the operating method further comprises: maintaining the two capacitors of the MSB and the one capacitor of the (MSB-1) of the first capacitor array to be grounded upon the first analog input being larger than the second analog input; and switching back the one capacitor of the (MSB-1) of the first capacitor array to the common voltage upon the first analog input being smaller than the second analog input.
15 . The operating method as claimed in claim 13 , wherein after the one of the two capacitors of the MSB of the first capacitor array is switched back to the common voltage, the operating method further comprises: maintaining the other one of the two capacitors of the MSB of the first capacitor array to be grounded, and the one of the two capacitors of the MSB and the one capacitor of the (MSB-1) of the first capacitor array to be coupled to the common voltage upon the first analog input being larger than the second analog input; and switching back both of the two capacitors of the MSB of the first capacitor array to the common voltage upon the first analog input being smaller than the second analog input.
16 . An operating method of an analog-to-digital converter, the analog-to-digital converter comprising a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator, a most significant bit (MSB) of each of the first capacitor array and the second capacitor array including four capacitors, a (MSB-1) of each of the first capacitor array and the second capacitor array including two capacitors, and a (MSB-2) of each of the first capacitor array and the second capacitor array including one capacitor, the operating method comprising: coupling the four capacitors of the MSB, the two capacitors of the (MSB-1) and the one capacitor of the (MSB-2) of each of the first and second capacitor arrays to a common voltage; grounding the four capacitors of the MSB of the first capacitor array upon a first analog input inputted into the non-inverting input terminal being larger than a second analog input inputted into the inverting input terminal; coupling the four capacitors of the MSB of the first capacitor array to a reference voltage upon the first analog input being smaller than the second analog input, wherein the reference voltage is 2 times of the common voltage; and controlling switches, coupled to capacitors among the first capacitor array and the second capacitor array but not coupled to the MSB, the (MSB-1) and the (MSB-2) of the first and second capacitor arrays, according to a fast binary window operation.
17 . The operating method as claimed in claim 16 , further comprising: coupling the four capacitors of the MSB of the second capacitor array to the reference voltage upon the four capacitors of the MSB of the first capacitor array being grounded; and grounding the four capacitors of the MSB of the second capacitor array upon the four capacitors of the MSB of the first capacitor array being coupled to the reference voltage.
18 . The operating method as claimed in claim 16 , wherein after the four capacitors of the MSB of the first capacitor array are grounded, the operating method further comprises: grounding the two capacitors of the (MSB-1) of the first capacitor array upon a difference between the first analog input and the second analog input being larger than ½ of the reference voltage; and switching back two of the four capacitors of the MSB of the first capacitor array to the common voltage upon the difference between the first analog input and the second analog input being smaller than ½ of the reference voltage.
19 . The operating method as claimed in claim 18 , wherein after the two capacitors of the (MSB-1) of the first capacitor array are grounded, the operating method further comprises: grounding the one capacitor of the (MSB-2) of the first capacitor array upon the difference between the first analog input and the second analog input being larger than ¾ of the reference voltage; and switching back one of the two capacitors of the (MSB-1) of the first capacitor array to the common voltage upon the difference between the first analog input and the second analog input being smaller than ¾ of the reference voltage.
20 . The operating method as claimed in claim 19 , wherein after the one capacitor of the (MSB-2) of the first capacitor array is grounded, the operating method further comprises: maintaining the four capacitors of the MSB, the two capacitors of the (MSB-1) and the one capacitor of the (MSB-2) of the first capacitor array to be grounded upon the difference between the first analog input and the second analog input being larger than ⅞ of the reference voltage; and switching back the one capacitor of the (MSB-2) of the first capacitor array to the common voltage upon the difference between the first analog input and the second analog input being smaller than ⅞ of the reference voltage.

Description

BACKGROUND 1. Field of the Disclosure The present disclosure generally relates to an analog-to-digital converter and, more particularly, to a successive approximation register analog-to-digital converter and an operating method thereof. 2. Description of the Related Art It is known that the integral nonlinearity (INL) and differential nonlinearity (DNL) can be used as indexes of evaluating the performance of an analog-to-digital converter (ADC). The INL and DNL can reflect the capacitor mismatch of a capacitor array in the ADC. A successive approximation register (SAR) ADC mainly uses a switchable capacitor array to approach an analog input, but the error occurs in switching capacitors in the capacitor array. It is known that the INL can be improved by using a fast binary window function in the SAR ADC. FIG. 1 is a schematic diagram of running the fast binary window function by an ADC converter, including switching zones and window zones. For example, FIG. 2 shows an operational schematic diagram of a differential ADC including three capacitors 4C, 2C and C, wherein it is assumed that analog inputs of the differential ADC are +0.3V and −0.3V. In the first conversion cycle, a code “1” is generated since Vp=+0.3>Vn=−0.3; in the second conversion cycle, the capacitor 4C is switched and a code “0” is generated since Vp=−0.2<Vn=+0.2; in the third conversion cycle, the capacitor 4C is switched back and the capacitor 2C is switched and a code “1” is generated since Vp=+0.05>Vn=−0.05; in the fourth conversion cycle, a code “1” is generated since Vp=+0.05>Vn=−0.05 and the capacitor 2C is not switched back; and in the fifth conversion cycle, the capacitor 1C is switched and a code “0” is generated since Vp=−0.075<Vn=+0.075, and the coding process is ended here, wherein Vp and Vn are input voltages of the differential ADC. The method of decoding the code “10110” is known to the art. However, the incorporation of the fast binary window function is not able to improve the DNL. Therefore, an ADC that may improve both the INL and DNL is required. The information disclosed in the Related Art herein is merely intended to increase understanding of the general background of the invention and should not be taken as an admission or in any way implied that the relevant information constitutes prior art that is already known to a person of ordinary skill in the art. SUMMARY Accordingly, the present disclosure provides an SAR ADC and an operating method thereof that improve both the INL and DNL by combining the fast binary window function and the thermal coding in the capacitor array. The present disclosure provides an SAR ADC and an operating method thereof that improve the INL by reducing a number of switched capacitors in the capacitor array. The present disclosure provides an SAR ADC and an operating method thereof that improve the DNL by replacing the most significant bit (MSB) capacitor with thermal coding capacitors. The present disclosure provides an analog-to-digital converter including a comparator and a first capacitor array. The first capacitor array is coupled to a first input terminal of the comparator, and includes a first most significant bit (MSB) and a first (MSB-1), wherein the first MSB includes multiple capacitors, the first (MSB-1) includes at least one capacitor, and capacitance of each of the multiple capacitors of the first MSB is identical to that of each of the at least one capacitor of the first (MSB-1). The present disclosure further provides an operating method of an analog-to-digital converter. The analog-to-digital converter includes a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator. The MSB of the first capacitor array and the second capacitor array respectively includes two capacitors and the (MSB-1) of the first capacitor array and the second capacitor array respectively includes one capacitor. The operating method includes the steps of: coupling the two capacitors of the MSB and the one capacitor of the (MSB-1) of the first and second capacitor arrays to a common voltage; grounding the two capacitors of the MSB of the first capacitor array upon a first analog input inputted into the non-inverting input terminal being larger than a second analog input inputted into the inverting input terminal; and coupling the two capacitors of the MSB of the first capacitor array to a reference voltage upon the first analog input being smaller than the second analog input, wherein the reference voltage is 2 times of the common voltage. The present disclosure further provides an operating method of an analog-to-digital converter. The analog-to-digital converter includes a comparator, a first capacitor array and a second capacitor array respectively coupled to a non-inverting input terminal and an inverting input terminal of the comparator. The MSB of the first capacitor array and the second c