US-12621001-B2 - Method and apparatus for SAR analog-to-digital conversion

Abstract

A successive approximation register (SAR) analog-to-digital converter (ADC) may be used to generate a first digital data of N-bit and a second digital data of N-bit for an analog data. When the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, a third digital data of N-bit may be generated for the analog data using the SAR ADC in a partial mode. In the partial mode, the SAR ADC is configured to skip determining a second sequence of MSBs of the third digital data, and only determine remaining bits of the third digital data. When the second digital data and the first digital data do not include the first sequence of MSBs having same values, the SAR ADC operates in a full mode to determine every bit of the N-bit third digital data.

Inventors

• Yen-Chang Tung

Assignees

• DIODES INCORPORATED

Dates

Publication Date

20260505

Application Date

20240520

Claims (20)

1. 1 . A method comprising: generating, by use of a successive approximation register (SAR) analog-to-digital converter (ADC), a first digital data of N-bit and a second digital data of N-bit for an analog data, wherein N is an integer greater than 1, and the analog data is a sampled data; and determining that the second digital data and the first digital data generated for the sampled data include a first sequence of most significant bits (MSBs) having same values, and based thereon, generating a third digital data of N-bit for the sampled data using the SAR ADC in a partial mode, in which the SAR ADC is configured to skip determining value(s) of a second sequence of MSBs of the third digital data.
2. 2 . The method of claim 1 , wherein generating the third digital data of N-bit in the partial mode comprises: setting value(s) of the second sequence of MSBs of the third digital data with respective value(s) of the second sequence of MSBs of the second digital data; and determining, using the SAR ADC, values of remaining bits of the third digital data.
3. 3 . The method of claim 2 , wherein the second sequence of MSBs comprises less number of bits than the first sequence of MSBs.
4. 4 . The method of claim 1 , further comprising: when the second digital data and the first digital data include the first sequence of MSBs having the same values, determining, based on whether a condition is satisfied, to generate the third digital data of N-bit for the analog data in the partial mode.
5. 5 . The method of claim 4 , wherein the condition is satisfied when a number of bits L of the first sequence of MSBs is greater than a threshold number W, L and W being integers between 1 and N.
6. 6 . The method of claim 5 , wherein the threshold number W is based on N.
7. 7 . The method of claim 5 , wherein the condition is satisfied when a pre-set number of digital data for the analog data have been generated.
8. 8 . The method of claim 1 , further comprising: when determining that the first digital data, the second digital data or the third digital data is invalid, re-generating the first digital data, the second digital data or the third digital data using the SAR ADC in a full mode, the full mode comprising determining every bit of a re-generated N-bit digital data using the SAR ADC.
9. 9 . The method of claim 1 , wherein the first digital data or the second digital data is generated using the SAR ADC in the partial mode or in a full mode, the full mode comprising determining every bit of a digital data using the SAR ADC.
10. 10 . The method of claim 1 , further comprising: determining a number of bits in the second sequence of MSBs based on N, a number of bits in the first sequence of MSBs, or a combination thereof.
11. 11 . The method of claim 1 , further comprising: when determining that the second digital data and the first digital data do not include the first sequence of MSBs having the same values, generating the third digital data of N-bit for the analog data using the SAR ADC in a full mode, the full mode comprising determining every bit of the third digital data using the SAR ADC.
12. 12 . The method of claim 1 , wherein the first digital data is an average of a plurality of digital data converted for the analog data.
13. 13 . The method of claim 1 , further comprising: generating a clock signal indicating the partial mode.
14. 14 . A method comprising: generating, by use of a successive approximation register (SAR) analog-to-digital converter (ADC), a first digital data and a second digital data for an analog data, the first digital data and the second digital data each having N bits; determining whether the second digital data includes a first sequence of bits having same values as the first sequence of bits of the first digital data, the first sequence of bits starting from a first most significant bit (MSB); when the second digital data includes the first sequence of bits having the same values as the first sequence of bits of the first digital data, determining, based on whether a condition is satisfied, whether to generate a third digital data of N bits for the analog data using the SAR ADC in a partial mode; and when the condition is satisfied, generating the third digital data in the partial mode, the generating comprising: setting value(s) of a second sequence of bits of the third digital data with respective value(s) of the second sequence of bits of the second digital data, the second sequence of bits starting from the first MSB, and the second sequence of bits comprising less than N bits; and determining values of remaining bits of the third digital data using the SAR ADC.
15. 15 . The method of claim 14 , wherein the second sequence of bits comprises less bits than the first sequence of bits.
16. 16 . The method of claim 14 , wherein the condition is satisfied when a number L of the first sequence of bits is greater than a threshold number, L and the threshold number being integers between 1 and N.
17. 17 . The method of claim 16 , wherein the condition is satisfied when a pre-set number of digital data for the analog data have been generated.
18. 18 . The method of claim 14 , further comprising: determining whether the third digital data is a valid digital data; and when the third digital data is invalid, switching to a full mode from the partial mode to re-generate the third digital data of N bits in the full mode, the full mode comprising determining every bit of the third digital data using the SAR ADC.
19. 19 . The method of claim 14 , wherein the first digital data or the second digital data is generated using the SAR ADC in the partial mode or in a full mode, the full mode comprising determining every bit of a digital data using the SAR ADC.
20. 20 . The method of claim 14 , further comprising: when the second digital data does not include the first sequence of bits having the same values as the first sequence of bits of the first digital data, generating the third digital data of N bits for the analog data using the SAR ADC in a full mode, the full mode comprising determining every bit of the third digital data using the SAR ADC.

Description

TECHNICAL FIELD The present disclosure relates generally to the field of analog-to-digital conversion, and in particular embodiments, to a method and apparatus for successive approximation register (SAR) analog-to-digital conversion. BACKGROUND Analog-to-digital converters (ADCs) are commonly used in digital electronics systems to convert analog signals into digital signals. The digital signals may further be processed by various digital processors such as digital audio processors, digital video processors, wireless communication processors, and the like. In some applications, ADCs may be implemented as standalone semiconductor devices, and in some other applications, ADCs may be integrated with other circuitry on a single integrated circuit. While various analog-to-digital architectures may be used, successive approximation register (SAR) ADCs are widely used in a variety of applications, such as battery-powered instruments, pen digitizers, industrial controls, multiplexed data acquisition, and so on. A SAR ADC performs a successive approximation algorithm (or sometimes referred to as “a binary search algorithm”) to output a digital signal. The SAR architecture provides moderate sample rates, medium resolutions, and high-performance with low-power consumption. SUMMARY Technical advantages are generally achieved, by embodiments of this disclosure which describe a method and apparatus for successive approximation register analog-to-digital conversion. In accordance with one aspect of the present disclosure, a method is provided that includes: generating, by use of a successive approximation register (SAR) analog-to-digital converter (ADC), a first digital data of N-bit and a second digital data of N-bit for an analog voltage, wherein N is an integer greater than 1; and when determining that the second digital data and the first digital data include a first sequence of most significant bits (MSBs) having same values, generating a third digital data of N-bit for the analog data using the SAR ADC in a partial mode, in which the SAR ADC is configured to skip determining value(s) of a second sequence of MSBs of the third digital data. In accordance with another aspect of the present disclosure, a method is provided that includes: generating, by use of a successive approximation register (SAR) analog-to-digital converter (ADC), a first digital data and a second digital data for an analog data, the first digital data and the second digital data each having N bits; determining whether the second digital data includes a first sequence of bits having same values as the first sequence of bits of the first digital data, the first sequence of bits starting from a first most significant bit (MSB); when the second digital data includes the first sequence of bits having the same values as the first sequence of bits of the first digital data, determining, based on whether a condition is satisfied, whether to generate a third digital data of N bits for the analog data using the SAR ADC in a partial mode; and when the condition is satisfied, generating the third digital data in the partial mode, the generating comprising: setting value(s) of a second sequence of bits of the third digital data with respective value(s) of the second sequence of bit of the second digital data, the second sequence of bits starting from the first MSB, and the second sequence of bits comprising less than N bits; and determining values of remaining bits of the third digital data using the SAR ADC. BRIEF DESCRIPTION OF THE DRAWINGS For a more complete understanding of the present disclosure, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which: FIG. 1 is a schematic block diagram of an example successive approximation register (SAR) analog-to-digital converter (ADC) according to a conventional technology; FIG. 2 is a diagram of waveforms showing an operation of the SAR ADC in FIG. 1; FIG. 3 is a schematic block diagram of an example capacitive DAC that may be used in the SAR ADC of FIG. 1; FIG. 4 is a flowchart of an example method for SAR analog-to-digital (A/D) conversion using a SAR ADC; FIG. 5 is a flowchart of an example method for SAR A/D conversion according to embodiments of the present disclosure; FIG. 6 is a flowchart of another example method for SAR A/D conversion according to embodiments of the present disclosure; FIG. 7 is a flowchart of yet another example method for SAR A/D conversion according to embodiments of the present disclosure; FIG. 8 is a block diagram of an example SAR ADC circuit according to embodiments of the present disclosure; and FIG. 9 is a block diagram of another example SAR ADC circuit according to embodiments of the present disclosure. Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of