US-12621003-B2 - Decoding method for reducing influence of noise of power signal line and decoding circuit

US12621003B2US 12621003 B2US12621003 B2US 12621003B2US-12621003-B2

Abstract

The preferred embodiment of the present disclosure relates to a decoding method for reducing the influence of noise power signal line and a decoding circuit. The method includes: dividing an analog signal to be decoded into a plurality of levels; performing an edge detection according to the levels to obtain a first edge detection signal; setting the levels which is smaller than a lower level to the lower level and performing the edge detection to obtain the second edge detection signal; setting the levels which is greater than a higher level to the higher level and performing the edge detection to obtain a third edge detection signal; decoding the first, the second, the third edge detection signal to obtain an optimum edge detection signal.

Inventors

Chih-Ming Chen
CHENG-CHUNG CHOU

Assignees

NUVOTON TECHNOLOGY CORPORATION

Dates

Publication Date: 20260505
Application Date: 20240920
Priority Date: 20240410

Claims (10)

1 . A decoding method for reducing influence of noise of power signal line, comprising: comparing a voltage level of an analog signal to be decoded with multiple reference voltages to generate a current level number; performing an edge detection process using the current level number at each time to obtain a first edge detection signal; after setting the current level number at each time that is less than a low-level number to the low-level number, performing the edge detection process to obtain a second edge detection signal; after setting the current level number at each time that is greater than a high-level number to the high-level number, performing the edge detection process to obtain a third edge detection signal; decoding the first edge detection signal, the second edge detection signal, and the third edge detection signal to obtain a first bit restored signal, a second bit restored signal, and a third bit restored signal, respectively, and comparing the first edge detection signal, the second edge detection signal, and the third edge detection signal with a bit time length to obtain an optimum bit restored signal, which has a smallest difference, among the first edge detection signal, the second edge detection signal, and the third edge detection signal; using the optimum bit restored signal to select an optimum edge detection signal from the first edge detection signal, the second edge detection signal, and the third edge detection signal as a specific edge detection signal for subsequent decoding, wherein the analog signal to be decoded is obtained from delivery of a known signal.
2 . The decoding method for reducing influence of noise of power signal line according to the claim 1 , wherein the edge detection process comprises: when the current level number is greater than a highest level variable, updating the highest level variable to the current level number; when the current level number is less than a lowest level variable, updating the lowest level variable to the current level number; when a difference between the lowest level variable and the highest level variable is greater than a noise tolerance value, outputting an edge detection pulse, setting the highest level variable and the lowest level variable to the current level number, and continuously determining a level of the analog signal to be decoded to obtain the current level number; and generating the specific edge detection signal based on the edge detection pulse.
3 . The decoding method for reducing influence of noise of power signal line according to the claim 1 , wherein the analog signal to be decoded is obtained via a channel configuration pin (CC pin) of a universal serial bus (USB) port.
4 . The decoding method for reducing influence of noise of power signal line according to the claim 1 , wherein the analog signal to be decoded is modulated according to a Bi-Phase Marker Code (BMC).
5 . The decoding method for reducing influence of noise of power signal line according to the claim 1 , wherein the known signal is a preamble signal.
6 . A decoding circuit, comprising: a plurality of comparators, wherein each of the plurality of comparators comprises a first terminal, a second terminal, and an output terminal, wherein the first terminals of the plurality of comparators receive an analog signal to be decoded, wherein the second terminals of the plurality of comparators are respectively coupled to a plurality of reference voltage levels, wherein the plurality of reference voltage levels are different from each other; and a noise filtering and signal edge detection circuit coupled to the output terminals of the plurality of comparators; wherein the noise filtering and signal edge detection circuit determines a current level of the analog signal to be decoded based on signals output from the output terminals of the comparators, to obtain a current level number; wherein the noise filtering and signal edge detection circuit performs an edge detection process based on the current level number at each time to obtain a first edge detection signal; wherein after setting the current level number at each time that is less than a low-level number to the low-level number, the noise filtering and signal edge detection circuit performs the edge detection process to obtain a second edge detection signal; wherein after setting the current level number at each time that is greater than a high-level number to the high-level number, the noise filtering and signal edge detection circuit performs the edge detection process to obtain a third edge detection signal; wherein the decoding circuit further comprises: a digital signal information processing circuit, coupled to the output terminals of the noise filtering and signal edge detection circuit, and configured to decode the first edge detection signal, the second edge detection signal, and the third edge detection signal to obtain a first bit restored signal, a second bit restored signal, and a third bit restored signal, respectively, and configured to compare the first edge detection signal, the second edge detection signal, and the third edge detection signal with a bit time length to obtain an optimum bit restored signal with a smallest difference; wherein the digital signal information processing circuit selects, based on the optimum bit restored signal, an optimum edge detection signal from the first edge detection signal, the second edge detection signal, and the third edge detection signal as a specific edge detection signal for subsequent decoding, wherein the analog signal to be decoded is obtained from delivery of a known signal.
7 . The decoding circuit according to the claim 6 , wherein the analog signal to be decoded is obtained via a channel configuration pin (CC pin) of a universal serial bus port.
8 . The decoding circuit according to the claim 6 , wherein the analog signal to be decoded is modulated based on a Bi-Phase Marker Code (BMC), and the digital signal information processing circuit is a BMC decoding circuit.
9 . The decoding circuit according to the claim 6 , wherein the noise filtering and signal edge detection circuit determines a current level of the analog signal to be decoded based on signals output by the output terminals of the comparators, to obtain the current level number, wherein the noise filtering and signal edge detection circuit has a highest level variable and a lowest level variable, wherein when the current level number is greater than the highest level variable, the highest level variable is updated to the current level number; wherein when the current level number is less than the lowest level variable, the lowest level variable is updated to the current level number, wherein when a difference between the lowest level variable and the highest level variable is greater than a noise tolerance value, the noise filtering and signal edge detection circuit outputs an edge detection pulse, sets the highest level variable and the lowest level variable to the current level number, and continuously determines a level of the analog signal to be decoded to obtain the current level number.
10 . The decoding circuit according to the claim 6 , wherein the known signal is a preamble signal.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims the priority from the TW Patent Application No. 113113422, filed on Apr. 10, 2024, and all contents of such TW Patent Application are comprised in the present disclosure. BACKGROUND 1. Field of the Invention The present disclosure is related to noise reduction technologies, and in particular to a decoding method for reducing the influence of noise power signal line and a decoding circuit. 2. Description of the Related Art Automatic charging is a popular device at the moment. The Universal Serial Bus Power Delivery (USB PD) protocol is currently the most widely used delivery specification. In addition to the main delivery interface charging and discharging through the VBUS pin, another related interface signal is on the CC pin. During data delivery (bit rate approximately 300K/s), the voltage level of the Channel Configuration pin (CC pin) is around 1.1V. Thus, any noise interference during the delivery process may affect the effectiveness of data reception during the message delivery process in the USB PD. The USB PD protocol not only includes power, but also handles the coordination of data flow direction, data formats, and master-slave relations between two devices. The USB PD protocol is transmitted through the CC pin, and when it is converted to a digital signal, its data packet also includes the calculation and comparison of cyclic redundancy checks (CRC) to prevent erroneous packet data caused by noise interference from being used. Thus, the known noise certification process also includes the following three different noise certification conditions: TX_NORMALTX_GROUP_1TX_GROUP_2TX_GROUP_3High_Level1100mV1200mV790mV1290mV(norm)Low_Level25mV0mV−25mV250mV(norm)Bit Rate300Kb/s270Kb/s330Kb/s330Kb/sRise/Fall Time735ns735ns735ns735ns Testing Noise Conditions It can be observed from the above three different noise certification conditions that the DC voltage level will drift upward or downward depending on different testing conditions. SUMMARY The present disclosure provides a method for reducing the influence of power signal line noise on decoding, a decoding circuit using the same, and a power supply/reception device using the same for adjusting the edge detection strategy prior to demodulation in a scenario where the signal is known, thereby overcoming the aforementioned noise conditions before subsequent carriers are demodulated into digital signals, ensuring correct decoding of the digital signal. Embodiments of the present disclosure provide a decoding method for reducing influence of noise of power signal line. The decoding method for reducing influence of noise of power signal line includes: comparing a voltage level of an analog signal to be decoded with multiple reference voltages to generate a current level number; performing an edge detection process using the current level number at each time to obtain a first edge detection signal; after setting the current level number at each time that is less than a low-level number to the low-level number, performing the edge detection process to obtain a second edge detection signal; after setting the current level number at each time that is greater than a high-level number to the high-level number, performing the edge detection process to obtain a third edge detection signal; decoding the first edge detection signal, the second edge detection signal, and the third edge detection signal to obtain a first bit restored signal, a second bit restored signal, and a third bit restored signal, respectively, and comparing the first edge detection signal, the second edge detection signal, and the third edge detection signal with a bit time length to obtain an optimum bit restored signal, which has a smallest difference, among the first edge detection signal, the second edge detection signal, and the third edge detection signal; using the optimum bit restored signal to select an optimum edge detection signal from the first edge detection signal, the second edge detection signal, and the third edge detection signal as a specific edge detection signal for subsequent decoding, wherein the analog signal to be decoded is obtained from delivery of a known signal. Embodiments of the present disclosure provide a decoding circuit. The decoding circuit includes: a plurality of comparators, a noise filtering and signal edge detection circuit, and a digital signal information processing circuit. Each of the plurality of comparators includes a first terminal, a second terminal, and an output terminal, wherein the first terminals of the plurality of comparators receive an analog signal to be decoded, wherein the second terminals of the plurality of comparators are respectively coupled to a plurality of reference voltage levels, wherein the plurality of reference voltage levels are different from each other. The noise filtering and signal edge detection circuit is coupled to the output terminals of the plurality of com