US-12621009-B2 - Memory, memory module, memory system, and operation method of memory system

US12621009B2US 12621009 B2US12621009 B2US 12621009B2US-12621009-B2

Abstract

A memory system may include an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode, and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode.

Inventors

Seok Woo Choi

Assignees

SK Hynix Inc.

Dates

Publication Date: 20260505
Application Date: 20240610
Priority Date: 20220715

Claims (16)

1 . A memory comprising: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; a first cell array configured to store the write data; a second cell array configured to store the first parity; and a third cell array configured to store the second parity.
2 . The memory of claim 1 , wherein the third cell array is configured to store therein or reads therefrom the second parity in the first error correction mode.
3 . The memory of claim 2 , further comprising an error correction circuit configured to: correct, in the first error correction mode, an error in the data read from the first cell array by using the first parity read from the second cell array and the second parity read from the third cell array; and correct, in the second error correction mode, the error in the read data by using the first parity read from the second cell array.
4 . The memory of claim 2 , further comprising an error correction circuit configured to perform an error correction operation, wherein the error correction circuit comprises: a first syndrome generation circuit configured to generate, in the respective first and second error correction modes, a first syndrome by using the data read from the first cell array and the first parity read from the second cell array; a second syndrome generation circuit configured to generate, in the first error correction mode, a second syndrome by using the read data and the second parity read from the third cell array; a first corrector configured to correct, in the first error correction mode, an error in the read data by using the first syndrome and the second syndrome; and a second corrector configured to correct, in the second error correction mode, the error in the read data by using the first syndrome.
5 . The memory of claim 4 , wherein the first corrector has a higher error correction capability than the second corrector.
6 . A memory module comprising: a module controller including: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; and a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; one or more first memories configured to store the write data; one or more second memories configured to store the first parity; and one or more third memories configured to store the second parity.
7 . The memory module of claim 6 , wherein the one or more third memories are configured to store therein or read therefrom the second parity in the first error correction mode.
8 . The memory module of claim 7 , further comprising an error correction circuit configured to perform an error correction operation, wherein the error correction circuit comprises: a first syndrome generation circuit configured to generate, in the respective first and second error correction modes, a first syndrome by using the data read from the one or more first memories and the first parity read from the one or more second memories; a second syndrome generation circuit configured to generate, in the first error correction mode, a second syndrome by using the read data and the second parity read from the one or more third memories; a first corrector configured to correct, in the first error correction mode, an error in the read data by using the first syndrome and the second syndrome; and a second corrector configured to correct, in the second error correction mode, the error in the read data by using the first syndrome.
9 . The memory module of claim 8 , wherein the first corrector has a higher error correction capability than the second corrector.
10 . A memory system comprising: a memory controller including: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; and a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; one or more first memories configured to store the write data; one or more second memories configured to store the first parity; and one or more third memories configured to store the second parity.
11 . The memory system of claim 10 , wherein the one or more third memories are configured to store therein or read therefrom the second parity in the first error correction mod.
12 . The memory system of claim 11 , further comprising an error correction circuit configured to perform an error correction operation, wherein the error correction circuit comprises: a first syndrome generation circuit configured to generate, in the respective first and second error correction modes, a first syndrome by using the data read from the one or more first memories and the first parity read from the one or more second memories; a second syndrome generation circuit configured to generate, in the first error correction mode, a second syndrome by using the read data and the second parity read from the one or more third memories; a first corrector configured to correct, in the first error correction mode, an error in the read data by using the first syndrome and the second syndrome; and a second corrector configured to correct, in the second error correction mode, the error in the read data by using the first syndrome.
13 . The memory system of claim 12 , wherein the first corrector has a higher error correction capability than the second corrector.
14 . The memory system of claim 11 , wherein the one or more first memories, the one or more second memories, and the one or more third memories are included in a memory module, and wherein the memory module further includes a plurality of buffers for transmitting the write data, the first parity, and the second parity between the one or more first memories, second memories, and third memories, and the memory controller.
15 . An operation method of a memory system, the operation method comprising: generating a first parity and a second parity corresponding to write data by using the write data to store the write data, the first parity, and the second parity in memory cells selected from a memory core by a write address during a write operation in a first error correction mode; reading data and the first parity from memory cells selected from the memory core by a read address to correct an error in the read data by using the read first parity during a read operation in a second error correction mode.
16 . The operation method of claim 15 , wherein the memory core includes a first region configured to store the write data, a second region configured to store the first parity, and a third region configured to store the second parity, and wherein the third region is configured to store therein or reads therefrom the second parity in the first error correction mode.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application is a division of U.S. patent application Ser. No. 17/986,968 filed on Nov. 15, 2022, and now issued as U.S. Pat. No. 12,034,457 on Jul. 9, 2024, which claims priority under 35 U.S.C. § 119 to Korean Patent Application No. 10-2022-0087315 filed on Jul. 15, 2022, which is incorporated herein by reference in its entirety. BACKGROUND 1. Field Embodiments of the present disclosure relate to a memory system. 2. Discussion of the Related Art In the early days of a semiconductor memory industry, a plurality of original good dies having no failed memory cell in a memory having passed through a semiconductor manufacturing process were distributed on a wafer. However, as the capacity of memory gradually increases, it has been difficult to manufacture a memory having no failed memory cell, and at the present time, it is safe to say that such a memory is no longer manufactural. As one measure of overcoming such a situation, a method of repairing failed memory cells of a memory with redundancy memory cells is being used. As another measure, a memory system uses an error correction circuit (ECC circuit) for correcting an error and corrects an error occurring in a memory cell and an error occurring while data is transmitted during read and write processes of the memory system. SUMMARY Various embodiments of the present disclosure are directed to providing a technique for improving the efficiency of error correction in a memory system. A memory system in accordance with an embodiment of the present disclosure may include: an error correction code generation circuit configured to generate a first error correction code having a large bit number by using write data and a first H matrix in a first error correction mode, and to generate a second error correction code having a small bit number by using the write data and a second H matrix in a second error correction mode; and a memory core configured to store the first error correction code and the write data in the first error correction mode, and to store the second error correction code and the write data in the second error correction mode. A memory in accordance with another embodiment of the present disclosure may include: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; a first cell array configured to store the write data; a second cell array configured to store the first parity; and a third cell array configured to store the second parity. A memory module in accordance with further another embodiment of the present disclosure may include: a module controller including: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; and a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; one or more first memories configured to store the write data; one or more second memories configured to store the first parity; and one or more third memories configured to store the second parity. A memory system in accordance with still another embodiment of the present disclosure may include: a memory controller including: a first parity generation circuit configured to generate a first parity by using write data in respective first and second error correction modes; and a second parity generation circuit configured to generate a second parity by using the write data in the first error correction mode; one or more first memories configured to store the write data; one or more second memories configured to store the first parity; and one or more third memories configured to store the second parity. An operation method of a memory system in accordance with yet another embodiment of the present disclosure may include: generating a first parity and a second parity corresponding to write data by using the write data to store the write data, the first parity, and the second parity in memory cells selected from a memory core by a write address during a write operation in a first error correction mode; reading data and the first parity from memory cells selected from the memory core by a read address to correct an error in the read data by using the read first parity during a read operation in a second error correction mode. An error correcting code (ECC) circuit in accordance with still yet another embodiment of the present disclosure may include: default and additional ECC generating circuits respectively configured to generate, based on default and additional H matrixes, default and additional ECCs for data to be stored in a storage medium; default and additional syndrome generating circuits respectively configured to generate, based on the def