US-12621013-B2 - Low complexity direct-to-LUT digital pre-distortion method

US12621013B2US 12621013 B2US12621013 B2US 12621013B2US-12621013-B2

Abstract

A distortion apparatus for a power amplifier comprises: pre-distortion circuitry that comprises a memory polynomial look-up-table (LUT) circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The pre-distortion circuitry comprises a plurality of LUTs. Each LUT corresponds to a different memory depth of a memory polynomial of a Volterra series. Each LUT indexed by an instantaneous power of an input sample delayed by an amount corresponds to a respective memory depth of each LUT. An output of the memory polynomial LUT circuit corresponds to a summation of an output of each LUT multiplied by the input sample delayed by the amount corresponding to the respective memory depth of each LUT, and an output of the pre-distortion circuitry is provided to the power amplifier.

Inventors

Paul Nicholas Fletcher
Donghan KIM
Fei Tong
Ziming He

Assignees

SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date: 20260505
Application Date: 20240125
Priority Date: 20230412

Claims (19)

1 . A distortion apparatus for a power amplifier, the distortion apparatus comprising: pre-distortion circuitry that comprises a memory polynomial circuit; post-distortion circuitry that is configured to update the pre-distortion circuitry based on an output of the power amplifier; and a Finite Impulse Response (FIR) filter that is configured to receive the output of the power amplifier and provide one or more inputs to the post-distortion circuitry, wherein the memory polynomial circuit comprises a plurality of LUTs, wherein each LUT of the memory polynomial circuit corresponds to a different memory depth of a memory polynomial of a Volterra series, wherein an instantaneous power of an input sample delayed by an amount that corresponds to a respective memory depth of each LUT is obtained by squaring an absolute value of the input sample delayed by the amount, wherein each LUT is indexed by the instantaneous power of the input sample delayed by the amount that corresponds to the respective memory depth of each LUT, wherein an output of the memory polynomial circuit corresponds to a summation of a coefficient output from each LUT multiplied by the input sample delayed by the amount corresponding to the respective memory depth of each LUT, and wherein an output of the pre-distortion circuitry is provided to the power amplifier, and wherein each LUT and coefficients of the FIR filter are updated together.
2 . The distortion apparatus according to claim 1 , wherein the pre-distortion circuitry comprises: a first cross-term circuit that comprises at least one LUT and is configured to receive a first delayed version of the input sample and a second delayed version of the input sample delayed by a different amount than the first delayed version of the input sample, wherein the at least one LUT is indexed based on an instantaneous power of the second delayed version of the input sample, and wherein an output of the first cross-term circuit corresponds to a multiplication of (i) a first exponential function applied to the first delayed version of the input sample with (ii) a coefficient output from the at least one LUT.
3 . The distortion apparatus according to claim 2 , wherein the pre-distortion circuitry comprises: a second cross-term circuit that comprises at least one LUT and is configured to receive the first delayed version of the input sample, the second delayed version of the input sample, and a third delayed version of the input sample that is delayed by a different amount than the first delayed version of the input sample and the second delayed version of the input sample, wherein the at least one LUT is indexed based on the instantaneous power of the second delayed version of the input sample, and wherein an output of the second cross-term circuit corresponds to a multiplication of (i) a second exponential function applied to the second delayed version of the input sample with (ii) a multiplication of the first exponential function applied to the first delayed version of the input sample with a coefficient output from the at least one LUT.
4 . The distortion apparatus according to claim 3 , wherein the output of the pre-distortion circuitry corresponds to a summation of the output of the memory polynomial, the output of the first cross-term circuit, and the output of the second cross-term circuit.
5 . The distortion apparatus according to claim 3 , wherein the post-distortion circuitry comprises: a post-distortion memory polynomial circuit that comprises a plurality of LUTs, wherein each LUT of the post-distortion memory polynomial circuit corresponds to a different memory depth of the memory polynomial of the Volterra series, wherein each LUT of the post-distortion memory polynomial circuit is indexed by one of (i) an instantaneous power of an output sample from the power amplifier delayed by an amount corresponding to a respective memory depth of each LUT and (ii) the instantaneous power of the input sample delayed by an amount corresponding to the respective memory depth of each LUT, and wherein an output of the post-distortion memory polynomial circuit corresponds to a summation of a coefficient output from each LUT multiplied by the output sample of the power amplifier delayed by the amount corresponding to the respective memory depth of each LUT.
6 . The distortion apparatus according to claim 5 , wherein the post-distortion circuitry comprises: a post-distortion first cross-term circuit that includes at least one LUT and is configured to receive the first delayed version of the output sample from the power amplifier and a second delayed version of the output sample from the power amplifier delayed by a different amount than the first delayed version of the output sample, wherein the at least one LUT of the post-distortion first cross-term circuit is indexed based on one of (i) an instantaneous power of the second delayed version of the output sample from the power amplifier or (ii) the instantaneous power of the input sample, and wherein an output of the post-distortion first cross-term circuit corresponds to a multiplication of (i) the first exponential function applied to the first delayed version of the output sample from the power amplifier with (ii) a coefficient output from the at least one LUT.
7 . The distortion apparatus according to claim 6 , wherein the pre-distortion circuitry comprises: a post-distortion second cross-term circuit that includes at least one LUT and is configured to receive: the first delayed version of the output sample from the power amplifier; the second delayed version of the output sample from the power amplifier; and a third delayed version of the output sample from the power amplifier delayed by a different amount than the first delayed version of the output sample and the second delayed version of the output sample, wherein the at least one LUT of the post-distortion second cross-term circuit is indexed based on one of (i) the instantaneous power of the second delayed version of the output sample from the power amplifier and (ii) the instantaneous power of the input sample, and wherein an output of the post-distortion second cross-term circuit corresponds to a multiplication of (i) a second exponential function applied to the second delayed version of the output sample from the power amplifier with (ii) a multiplication of the first exponential function applied to the first delayed version of the output sample from the power amplifier with a coefficient output from the at least one LUT.
8 . The distortion apparatus of claim 7 , further comprising an error calculation block configured to compute an error based on a difference between (i) a sum of the post-distortion memory polynomial circuit, (ii) the post-distortion first cross-term circuit, and the post-distortion second cross-term circuit and (iii) the output of the pre-distortion circuitry, wherein the post-distortion circuitry is configured to update each LUT based on the computed error.
9 . The distortion apparatus of claim 8 , wherein the post-distortion circuitry is configured to update each LUT based on the computed error on a sample by sample basis.
10 . The distortion apparatus of claim 9 , wherein the post-distortion circuitry is configured to update each LUT based on the computed error on a batch of samples.
11 . The distortion apparatus of claim 3 , wherein the post-distortion circuitry comprises: a post-distortion memory polynomial circuit that comprises a plurality of LUTs, each LUT corresponding to a different memory depth of the memory polynomial of the Volterra series, each LUT indexed by the instantaneous power of the second delayed version of the input sample; a post-distortion first cross-term circuit that comprises at least one LUT that is indexed by the instantaneous power of the second delayed version of the input sample; and a post-distortion second cross-term circuit that comprises at least one LUT that is indexed by the instantaneous power of the second delayed version of the input sample.
12 . The distortion apparatus of claim 11 , further comprising an error calculation block configured to compute an error based on a difference between the output of the power amplifier and the input sample.
13 . The distortion apparatus of claim 12 , wherein the post-distortion circuitry is configured to update each LUT of the post-distortion memory polynomial circuit based on a multiplication of the computed error with the second delayed version of the input sample.
14 . The distortion apparatus of claim 12 , wherein the post-distortion circuitry is configured to update the at least one LUT of the post-distortion first cross-term circuit based on a multiplication of the computed error with the first exponential function applied to the first delayed version of the input sample.
15 . The distortion apparatus of claim 12 , wherein the post-distortion circuitry is configured to update the at least one LUT of the post-distortion second cross-term circuit based on a multiplication of the computed error with a multiplication of (a) the first exponential function applied to the first delayed version of the input sample with (b) the second exponential function applied to the third delayed version of the input sample.
16 . The distortion apparatus of claim 15 , wherein the post-distortion circuitry is configured to update each LUT in the post-distortion circuitry based on the computed error on a sample by sample basis.
17 . The distortion apparatus of claim 15 , wherein the post-distortion circuitry is configured to update each LUT in the post-distortion circuitry based on the computed error on a batch of samples.
18 . A distortion apparatus for a power amplifier, the distortion apparatus comprising: pre-distortion circuitry that comprises a cross-term circuit; post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier; and a Finite Impulse Response (FIR) filter that is configured to receive the output of the power amplifier and provide one or more inputs to the post-distortion circuitry, wherein the cross-term circuit comprises at least one LUT and is configured to receive a first delayed version of an input sample and a second delayed version of the input sample delayed by a different amount than the first delayed version of the input sample, wherein an instantaneous power of the second delayed version of the input sample is obtained by squaring an absolute value of the second delayed version of the input sample, wherein the at least one LUT is indexed based on the instantaneous power of the second delayed version of the input sample, wherein an output of the cross-term circuit corresponds to a multiplication of (i) a first exponential function applied to the first delayed version of the input sample with (ii) a coefficient output from the at least one LUT, and wherein each LUT and coefficients of the FIR filter are updated together.
19 . A distortion apparatus for a power amplifier, the distortion apparatus comprising: pre-distortion circuitry that comprises a cross-term circuit; post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier; and a Finite Impulse Response (FIR) filter that is configured to receive the output of the power amplifier and provide one or more inputs to the post-distortion circuitry, wherein the cross-term circuit comprises at least one LUT and is configured to receive a first delayed version of an input sample, a second delayed version of the input sample, and a third delayed version of the input sample that is delayed by a different amount than the first delayed version of the input sample and the second delayed version of the input sample, wherein an instantaneous power of the second delayed version of the input sample is obtained by squaring an absolute value of the second delayed version of the input sample, wherein the at least one LUT is indexed based on the instantaneous power of the second delayed version of the input sample, wherein an output of the cross-term circuit corresponds to a multiplication of (i) a second exponential function applied to the second delayed version of the input sample with (ii) a multiplication of a first exponential function applied to the first delayed version of the input sample with a coefficient output from the at least one LUT, and wherein each LUT and coefficients of the FIR filter are updated together.

Description

CROSS-REFERENCE TO RELATED APPLICATION This application claims priority to Korean Patent Application No. 10-2023-0048176, filed on Apr. 12, 2023, the disclosures of each of which are incorporated by reference herein their entirety. TECHNICAL FIELD This disclosure is directed to pre-distortion circuitry that applies a direct-to-LUT digital pre-distortion method to a power amplifier. BACKGROUND A wireless transmitter includes a power amplifier (PA) that provides a final level of amplification of a radio frequency (RF) signal. The PA must provide sufficient amplification of the signal such that when radiated from an antenna of the wireless transmitter, the signal is at a power level that is sufficient to reach an antenna of a receiver so that data encoded in a modulated RF signal can be correctly decoded. Furthermore, it is desirable for the PA to operate in a condition where it is power efficient (e.g., provides a power amplification to the signal without consuming or wasting power itself). Regardless of the type of PA (e.g. class, semi-conductor make-up), to maximize power efficiency, it is necessary to operate the PA close to a compression region, which is a region of the PA characteristic where high signal amplitude peaks are distorted by the PA's inability to provide sufficient power. Modern wireless modulation formats are a non-constant envelope with a peak-to-average power ratio (PAPR) in excess of 10 dB not being uncommon. Operating the PA at a power level such that the peaks of the signal do not enter the compression region and undergo distortion mandates that the PA must be operated in a so-called ‘backed off’ state, which results in the PA operating in a highly inefficient manner, thereby leading to non-optimal transmission from the wireless transmitter. SUMMARY According to one or more embodiments, a distortion apparatus for a power amplifier comprises: pre-distortion circuitry that comprises a memory polynomial look-up-table (LUT) circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The pre-distortion circuitry comprises a plurality of LUTs. Each LUT corresponds to a different memory depth of a memory polynomial of a Volterra series. Each LUT indexed by an instantaneous power of an input sample delayed by an amount corresponds to a respective memory depth of each LUT. An output of the memory polynomial LUT circuit corresponds to a summation of an output of each LUT multiplied by the input sample delayed by the amount corresponding to the respective memory depth of each LUT, and an output of the pre-distortion circuitry is provided to the power amplifier. According to one or more embodiments a distortion apparatus for a power amplifier, comprising: pre-distortion circuitry that comprises a cross-term circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The cross-term circuit comprises at least one LUT and is configured to receive a first delayed version of an input sample and a second delayed version of the input sample delayed by a different amount than the first delayed version of the input sample. The at least one LUT is indexed based on an instantaneous power of the second delayed version of the input sample. An output of the first cross-term circuit corresponds to a multiplication of (i) a first exponential function applied to the first delayed version of the input sample with (ii) an output of the at least one LUT. According to one or more embodiments, the distortion apparatus comprising: pre-distortion circuitry that comprises a cross-term circuit; and post-distortion circuitry that updates the pre-distortion circuitry based on an output of the power amplifier. The cross-term circuit comprises at least one LUT and is configured to receive the first delayed version of the input sample, a second delayed version of the input sample, and a third delayed version of the input sample that is delayed by a different amount than first delayed version of the input sample and the second delayed version of the input sample. The at least one LUT is indexed based on the instantaneous power of the second delayed version of the input sample. An output of the second cross-term circuit corresponds to a multiplication of (i) the first exponential function applied to the first delayed version of the input sample with (ii) the output of the at least one LUT, and with (iii) a second exponential function applied to the second delayed version of the input sample. BRIEF DESCRIPTION OF DRAWINGS Further features, the nature, and various advantages of the disclosed subject matter will be more apparent from the following detailed description and the accompanying drawings in which: FIG. 1 is a schematic illustration of an indirect learning pre-distortion architecture, in accordance with embodiments of the present disclosure. FIG. 2 is a schematic illustration of a closed-loop pre-di