US-12621175-B2 - Computing apparatus for proof of work, and ASIC chip and computing method for proof of work

US12621175B2US 12621175 B2US12621175 B2US 12621175B2US-12621175-B2

Abstract

A computing apparatus and method for proof of work, and a chip are provided. The computing apparatus includes: N selectors, respectively configured to obtain N groups of first input quantities; and N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each first compressor is configured to sequentially perform compression processing on the second input quantity and each first input quantity in one group of first input quantities, and compression processing results of the N first compressors each is used to obtain a proof-of-work result.

Inventors

Xufeng Wu
Cunyong Yang
Ketuan Zhan

Assignees

BITMAIN TECHNOLOGIES INC.

Dates

Publication Date: 20260505
Application Date: 20230815
Priority Date: 20210220

Claims (16)

1 . A computing apparatus for proof of work, comprising: N selectors, respectively configured to obtain N groups of first input quantities, wherein N is a positive integer greater than 1, wherein each of the N groups of first input quantities includes k first input quantities, k is a positive integer greater than 1; N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each of the N first compressors is configured to perform compression processing on the second input quantity and the first input quantities in a respective one of the N groups of first input quantities sequentially, and compression processing results of the N first compressors each is used to obtain a proof-of-work result; and N adders, respectively connected to the N first compressors, wherein each of the N adders is configured to perform addition processing on a compression processing result of a respective first compressor of the N first compressors and a group of delayed first input quantities corresponding to the respective first compressor, wherein the N groups of first input quantities are generated by a first generator, and N groups of delayed first input quantities are generated by a second generator, the first generator and the second generator are different mid-state generators, wherein the N selectors, the N first compressors and the N adders are disposed on an ASIC chip disposed on a computing power board, the first generator and the second generator are disposed on a control board.
2 . The computing apparatus according to claim 1 , wherein the N groups of delayed first input quantities are input to their corresponding adders by additional N selectors, respectively.
3 . The computing apparatus according to claim 1 , wherein each group of first input quantities is generated by the first generator according to different version numbers in a block header, and each group of delayed first input quantities is generated by the second generator according to the different version numbers in the block header.
4 . The computing apparatus according to claim 1 , wherein the second input quantity comprises a message field of a block header, and the message field comprises at least one of the following: last 32 bits of a hash Merkle root, a timestamp, a difficulty, a nonce, or a padding bit.
5 . The computing apparatus according to claim 4 , further comprising: a first expander, configured to perform expansion processing on a mid-state field, to obtain the second input quantity, wherein the first expander is disposed on an ASIC (Application Specific Integrated Circuits) chip.
6 . The computing apparatus according to claim 1 , wherein the first input quantity comprises a mid-state field of a block header, and the mid-state field comprises at least one of the following: a version number, a hash value of a previous block, or first 224 bits of a hash Merkle root.
7 . The computing apparatus according to claim 6 , further comprising: N second expanders, respectively configured to perform expansion processing on N candidate values of the message field, wherein the N second expanders are disposed on an ASIC chip disposed on the computing power board; and N second compressors, respectively connected to the N second expanders, and respectively configured to perform compression processing on expansion processing results of the N candidate values of the message field, to obtain the N groups of first input quantities, wherein the N second compressors are disposed on an ASIC chip disposed on the computing power board.
8 . The computing apparatus according to claim 1 , further comprising: N third expanders, respectively connected to the N adders, and respectively configured to perform expansion processing on addition processing results of the N adders, wherein the N third expanders are disposed on an ASIC chip; and N third compressors, respectively connected to the N third expanders, and respectively configured to perform compression processing on expansion processing results of the N third expanders, to obtain the proof-of-work result, wherein the N third compressors are disposed on an ASIC chip.
9 . An application-specific integrated circuit (ASIC) chip, comprising a computing apparatus for proof of work, wherein the computing apparatus comprising: N selectors, respectively configured to obtain N groups of first input quantities, wherein N is a positive integer greater than 1, wherein each of the N groups of first input quantities includes k first input quantities, k is a positive integer greater than 1; N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each of the N first compressors is configured to perform compression processing on the second input quantity and the first input quantities in a respective one of the N groups of first input quantities sequentially, and compression processing results of the N first compressors each is used to obtain a proof-of-work result; and N adders, respectively connected to the N first compressors, wherein each of the N adders is configured to perform addition processing on a compression processing result of a respective first compressor of the N first compressors and a group of delayed first input quantities corresponding to the respective first compressor, wherein the N groups of first input quantities are generated by a first generator, and N groups of delayed first input quantities are generated by a second generator, the first generator and the second generator are different mid-state generators, wherein the N selectors, the N first compressors and the N adders are disposed on an ASIC chip disposed on a computing power board, the first generator and the second generator are disposed on a control board.
10 . A computing method for proof of work, comprising: obtaining, by N selectors, N groups of first input quantities, respectively, wherein N is a positive integer greater than 1, wherein each of the N groups of first input quantities includes k first input quantities, k is a positive integer greater than 1; receiving, by N first compressors connected to the N selectors, the N groups of first input quantities sent by the N selectors and a same second input quantity, respectively, and performing, by each of the N first compressors, compression processing on the second input quantity and the first input quantities in a respective one of the N groups of first input quantities sequentially; obtaining a proof-of-work result according to compression processing results of the N first compressors; and performing, by each of N adders respectively connected to the N first compressors, addition processing on a compression processing result of a respective first compressor of the N first compressors and a group of delayed first input quantities corresponding to the respective first compressor, wherein the N groups of first input quantities are generated by a first generator, and N groups of delayed first input quantities are generated by a second generator, the first generator and the second generator are different mid-state generators, wherein the N selectors, the N first compressors and the N adders are disposed on an ASIC chip disposed on a computing power board, the first generator and the second generator are disposed on a control board.
11 . The computing method according to claim 10 , wherein the N groups of delayed first input quantities are input to their corresponding adders by additional N selectors, respectively.
12 . The computing method according to claim 10 , wherein each group of first input quantities is generated by the first generator according to different version numbers in a block header, and each group of delayed first input quantities is generated by the second generator according to the different version numbers in the block header.
13 . The computing method according to claim 10 , wherein the second input quantity comprises a message field of a block header, and the message field comprises at least one of the following: last 32 bits of a hash Merkle root, a timestamp, a difficulty, a nonce, or a padding bit.
14 . The computing method according to claim 13 , further comprising: performing, by a first expander, expansion processing on a mid-state field, to obtain the second input quantity.
15 . The computing method according to claim 10 , wherein the first input quantity comprises a mid-state field of a block header, and the mid-state field comprises at least one of the following: a version number, a hash value of a previous block, or first 224 bits of a hash Merkle root.
16 . The computing method according to claim 15 , further comprising before the obtaining, by N selectors, N groups of first input quantities, respectively: performing, by N second expanders, expansion processing on N candidate values of the message field, respectively; and performing, by N second compressors connected to the N second expanders, compression processing on expansion processing results of the N candidate values of the message field, respectively, to obtain the N groups of first input quantities.

Description

CROSS-REFERENCE TO RELATED APPLICATION The present application is a U.S. continuation under 35 U.S.C. § 111(a) of International Application No. PCT/CN2022/071658 filed on Jan. 12, 2022, which claims priority to Chinese Patent Application No. 202110196725.2, filed with the China National Intellectual Property Administration on Feb. 20, 2021, and entitled “COMPUTING APPARATUS FOR PROOF OF WORK, ASIC CHIP, AND COMPUTING METHOD FOR PROOF OF WORK”. The contents of these applications are incorporated herein by reference in their entirety for all purposes. TECHNICAL FIELD The present disclosure relates to the field of data processing. BACKGROUND A proof-of-work process is a process of finding a nonce that meets a condition within a specific range through a large amount of computing, and its nature is to “solve” a current block through competition. A node that solves the block first may gain a corresponding reward. Therefore, how to improve the computing efficiency of proof of work becomes an urgent problem to be solved. SUMMARY Embodiments of the present application provide a computing apparatus for proof of work, an ASIC chip, and a computing method for proof of work. According to an aspect, an embodiment of the present application provides a computing apparatus for proof of work. The computing apparatus includes N selectors, respectively configured to obtain N groups of first input quantities, wherein N is a positive integer greater than 1; and N first compressors, respectively connected to the N selectors, and respectively configured to receive the N groups of first input quantities sent by the N selectors, and to receive a same second input quantity, wherein each first compressor is configured to sequentially perform compression processing on the second input quantity and each first input quantity in one group of first input quantities, and compression processing results of the N first compressors each are used to obtain a proof-of-work result. According to another aspect, an embodiment of the present application provides a chip. The chip includes the computing apparatus in the above aspect. According to yet another aspect, an embodiment of the present application provides a computing method for proof of work. The computing method includes obtaining, by N selectors, N groups of first input quantities, respectively, where N is a positive integer greater than 1; receiving, by N first compressors connected to the N selectors, the N groups of first input quantities sent by the N selectors and a same second input quantity, respectively, and performing, by each first compressor, compression processing on the second input quantity and each first input quantity in one group of first input quantities sequentially; and obtaining a proof-of-work result according to compression processing results of the N first compressors. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic diagram of a blockchain; FIG. 2 is a schematic diagram of a Merkle Tree; FIG. 3 is a schematic diagram of a computing process of proof of work; FIG. 4 is a schematic diagram of a loop in a conventional computing process of proof of work; FIG. 5 is a schematic diagram of a loop in an ASIC-BOOST-based computing process of proof of work; FIG. 6 is a schematic diagram of a computing apparatus for proof of work according to an embodiment of the present application; FIG. 7 is a schematic diagram of a computing principle for proof of work according to an embodiment of the present application; and FIG. 8 is a schematic flowchart of a computing method for proof of work according to an embodiment of the present application. DETAILED DESCRIPTION OF EMBODIMENTS The technical solutions of the present application will be described below with reference to the accompanying drawings. To better understand the embodiments of the present application, the principle of proof of work is first described. A proof-of-work process may also be referred to as a “mining” process, the core of which is to perform a large amount of computing using a plurality of computing platforms (also referred to as “mining machines”), to find a nonce that meets a condition within a specific range. The nature of the process is to “solve” a current block through competition. A new reward is generated each time a block is solved, and can be gained only by a node that solves the block first. Each block contains one record, and an address in the record is an address that is qualified to gain the reward. This record is referred to as a production transaction. In a network, data is permanently recorded in the form of files, which are referred to as blocks. One block is a set of records for some or all of the latest production transactions, for example, all transactions within ten minutes that are not recorded in another previous block. Each block records all events that occurred before the block is created. As shown in Table 1, the block usually includes a magic number (Magic No), a block size (Bloc