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US-12621186-B2 - Switch matrix topology for routing high frequency signals

US12621186B2US 12621186 B2US12621186 B2US 12621186B2US-12621186-B2

Abstract

A switch matrix structure for planar circuitry such as printed circuit boards and integrated circuits includes a plurality of signal dividers and a plurality of switches. Each signal divider is configured to receive a corresponding input signal and generate a corresponding plurality of divider output signals. Each switch is configured to receive a corresponding divider output from a corresponding signal divider. Each switch is configured to provide a corresponding output signal such that a plurality of output signals are generated by the plurality of switches. In an example, the plurality of switches are arranged in a column, with a first subset of the plurality of signal dividers on a first side of the column, and a second subset of the plurality of signal dividers on a second side of the column. In an example, such a routing configuration reduces a number of routing layers and/or a number of via transitions.

Inventors

  • Randall T. Enderby
  • Jake H. Rivard

Assignees

  • BAE SYSTEMS INFORMATION AND ELECTRONIC SYSTEMS INTEGRATION INC.

Dates

Publication Date
20260505
Application Date
20230627

Claims (12)

  1. 1 . A switch matrix for planar circuitry, the switching matrix comprising: a plurality of signal dividers, each signal divider configured to receive a corresponding input signal and generate a corresponding plurality of divider output signals; a plurality of switches, each switch configured to receive a corresponding divider output from a corresponding signal divider, such that each switch receives a corresponding plurality of divider output signals from the plurality of signal dividers, wherein each switch is configured to provide a corresponding output signal such that a plurality of output signals are generated by the plurality of switches; and a plurality of routing layers, each routing layer comprising a corresponding layer of dielectric material and a corresponding plurality of interconnect features extending within the layer of dielectric material, wherein the interconnect features of the routing layers couple the plurality of the signal dividers to the plurality of switches; wherein the plurality of switches are arranged in a group, with a first subset of the plurality of signal dividers on a first side of the group, and a second subset of the plurality of signal dividers on a second side of the group; wherein the plurality of routing layers comprise a first routing layer adjacent to a second routing layer, with no routing layers between the first and second routing layers, and wherein the switch matrix further comprises: a conductive material extending between the first routing layer and the second routing layer, the conductive material configured to be grounded.
  2. 2 . The switch matrix of claim 1 , wherein the first side of the group is opposite the second side of the group, and wherein no switches of the plurality of switches are on any other side of the group, except the first and second sides of the group.
  3. 3 . The switch matrix of claim 1 , wherein the conductive material comprises a ground plane between the first routing layer and the second routing layer, and wherein the signal dividers are radio frequency (RF) signal dividers and the switches are RF switches.
  4. 4 . The switch matrix of claim 1 , further comprising: a conductive via structure coupled between a first interconnect feature within the first routing layer and a second interconnect feature within the second routing layer, wherein the via extends through an opening within the conductive material, without contacting the conductive material.
  5. 5 . The switch matrix of claim 1 , wherein: the plurality of routing layers includes at least an upper routing layer, and a lower routing layer below the upper routing layer; the first subset of the plurality of signal dividers on the first side of the group includes at least a first signal divider and a second signal divider; the second subset of the plurality of signal dividers on the second side of the group includes at least a third signal divider and a fourth signal divider; and the first and third signal dividers are on the upper routing layer, and the second and fourth signal dividers are on the lower routing layer.
  6. 6 . The switch matrix of claim 5 , wherein: a first switch of the plurality of switches is on the upper routing layer; a first divider output signal from the first signal divider to the first switch and a third divider output signal from the third signal divider to the first switch are routed entirely through the upper routing layer and not through any other routing layer; and a second divider output signal from the second signal divider to the first switch and a fourth divider output signal from the fourth signal divider to the first switch are routed through the upper and lower routing layers.
  7. 7 . The switch matrix of claim 6 , wherein: the plurality of routing layers further includes an intermediate routing layer between the upper and lower routing layers; and the second divider output signal and the fourth divider output signal are further routed through the intermediate routing layer.
  8. 8 . The switch matrix of claim 1 , wherein: a number of routing layers within the plurality of routing layers is N L , and a number of signal dividers within the plurality of signal dividers is N i ; and N L is equal to ┌N i /2┐, where └ . . . ┐ represents the ceiling function.
  9. 9 . The switch matrix of claim 1 , wherein the group of switches includes or is a column of switches, and wherein: the first side of the column is opposite the second side of the column; a third side of the column is perpendicular to the first side of the column, and a fourth side of the column is opposite the third side of the column; and a plurality of outputs from the plurality of switches are routed towards the third or fourth side of the column, and not towards the first or second side of the column.
  10. 10 . The switch matrix of claim 1 , wherein: the group of switches are arranged along a horizontal plane; a first switch of the group of switches has (i) one or more second switches on a first side (ii) one or more third switches on a second side opposite the first side, and (iii) no switches on a third side and a fourth side that are perpendicular to the first and second sides; and the first, second, third, and fourth sides of the first switch are on the horizontal plane.
  11. 11 . A printed circuit board (PCB) or printed wiring board (PWB) comprising the switch matrix of claim 1 .
  12. 12 . A method of forming a switch matrix, comprising: forming a plurality of routing layers including at least a first routing layer and a second routing layer, wherein one of the first and second routing layers is an uppermost routing layer of the plurality of routing layers, and the other of the first and second routing layers is a lowermost routing layer of the plurality of routing layers; arranging a plurality of switches in a column and on the first routing layer; and arranging a plurality of signal dividers, such that a first signal divider and a second signal divider of the plurality of signal dividers are on a first side of the column, and a third signal divider and a fourth signal divider of the plurality of signal dividers are on a second side of the column, wherein the first and third signal dividers are on the first routing layer, and the second and fourth signal dividers are on the second routing layer; wherein the plurality of routing layers comprise a plurality of interconnect features to couple each switch of the plurality of switches of each signal divider of the plurality of signal dividers; wherein a number of routing layers within the plurality of routing layers is N L , and a number of signal dividers within the plurality of signal dividers is N i ; and N L is equal to ┌N i /2┐, where ┌ . . . ┐ represents the ceiling function.

Description

TECHNICAL FIELD The present disclosure relates generally to switch matrix topology, and more particularly to switch matrix topology for routing high frequency signals, such as radio frequency (RF) signals and/or microwave signals. BACKGROUND Radio frequency (RF) signals are widely used in a number of applications. Often times, RF applications require reconfigurable routing of multiple input signals to various receivers (or multiple output signals to various transmitters). A switch matrix (SM) circuit may be employed to implement such reconfigurable routing of the RF signals. For example, a switch matrix circuit may include a plurality of inputs and a plurality of outputs, where any output may receive any of the input signal. In an example, to implement RF signaling of the switch matrix, a plurality of routing layers of a circuit board (such as a printed circuit board or PCB) may be used. There remain several non-trivial issues with respect to designing and forming routing layout for a switch matrix. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 illustrates a routing layout of a switch matrix having reduced number of routing layers and reduced via transitions between adjacent routing layers, in accordance with an embodiment of the present disclosure. FIG. 2 illustrates an operation of the switch matrix, in accordance with an embodiment of the present disclosure. FIG. 3A illustrates a planar circuit structure comprising a plurality of routing layers including a plurality of interconnect features (such as conductive vias and conductive lines), wherein the interconnect features route various signals of the switch matrix of FIGS. 1 and 2, in accordance with an embodiment of the present disclosure. FIG. 3B illustrates another planar circuit structure that is at least in part similar to the planar circuit structure of FIG. 3A, where the planar circuit structure of FIG. 3B has a higher number of routing layers than the planar circuit structure of FIG. 3A, in accordance with an embodiment of the present disclosure. FIG. 3C-3E illustrate various example arrangements of switches relative to signal dividers of a switch matrix, in accordance with an embodiment of the present disclosure. FIG. 4 illustrates a routing layout of an example switch matrix having eight input signals, four output signals, and four routing layers, in accordance with an embodiment of the present disclosure. FIG. 5 illustrates a routing layout of an example switch matrix having four input signals, eight output signals, and two routing layers, in accordance with an embodiment of the present disclosure. FIG. 6 illustrates a routing layout of an example switch matrix having six input signals, four output signals, and three routing layers, in accordance with an embodiment of the present disclosure. FIG. 7 illustrates a flowchart depicting a method of forming a switch matrix (such as any of the switch matrices of FIGS. 1-6), in accordance with an embodiment of the present disclosure. The figures depict various embodiments of the present disclosure for purposes of illustration only and are not necessarily drawn to scale. Numerous variations, configurations, and other embodiments will be apparent from the following detailed discussion. DETAILED DESCRIPTION A switch matrix for routing signals is described herein. In an example, the switch matrix has a routing layout that reduces a number of routing layers and/or a number of via transitions used to implement the switch matrix, relative to a traditional switch matrix. The switch matrix may be used to route any type of signals, and may be especially advantageous to route radio frequency (RF) signals, where reducing a number of routing layers, reducing a number of via transitions, and/or reducing a number of cross-overs (e.g., where one RF line crosses over another signal line in close proximity to cause parasitic capacitance or cross-talk between those two lines) can substantially reduce RF signal losses. Because of the reduced number of routing layers, the reduced number of via transitions and/or reduced cross-overs, RF signal losses in the switch matrix is relatively lower, thereby increasing performance of the switch matrix. Furthermore, circuit board cost and complexity may also be reduced. In an embodiment, a switch matrix for planar circuitry (such as a printed circuit board or integrated circuit), comprises a plurality of signal dividers, where each signal divider is configured to receive a corresponding input signal and generate a corresponding plurality of divider output signals. The switch matrix further includes a plurality of switches. In some examples, each switch is configured to receive a corresponding divider output from a corresponding signal divider, such that each switch receives a corresponding plurality of divider output signals from the plurality of signal dividers. In some such examples, each switch is configured to provide a corresponding output signal such that a plurality of output signa