Search

US-12621238-B2 - Network-on-chip packetization and routing method and apparatus for scalable high-performance networking on and off chip

US12621238B2US 12621238 B2US12621238 B2US 12621238B2US-12621238-B2

Abstract

The present invention discloses a computer-implemented method of data transmission for a Network-on-Chip to allow high performance routing through dynamic allocated buffer. The method comprises the steps of transferring command or data in a form of plurality of flits from a source node to a router and further to a destination node, and transmitting the flits from the destination node back to the router, wherein the flits are packetized for transmission according to channel width and transaction width, sequence, and priority routing through physical and virtual channels.

Inventors

  • Chee Hak Teh
  • Yu Ying Ong
  • Soon Chieh Lim
  • Weng Li Leow
  • Yeong Tat Liew
  • Chuen Heong KHUAN
  • Manobindra GANDHI
  • MUHAMAD AIDIL BIN JAZMI

Assignees

  • SKYECHIP SDN BHD

Dates

Publication Date
20260505
Application Date
20230614
Priority Date
20230301

Claims (9)

  1. 1 . A computer-implemented method of data transmission for a Network-on-Chip, characterized in that said method comprises the steps of: transferring command or data in a form of a plurality of flits from a source node to a router through one or more physical channels; transmitting the flits from the router to a destination node through one or more physical channels by: distributing the flits to a plurality of virtual channel First In First Out (FIFOs); multiplexing the virtual channel FIFOs for flits entering the destination node; spanning the flits into multiple flits if the physical channel that the virtual channel resides in has a channel width that is less than the transaction flit width, and incrementing the multiple flits until the end-of-packet before passing on to the next FIFO to a downstream destination node; transmitting the flits from the destination node to the router through one or more physical channels by: splitting the flits into multiple cycles based on the width of the physical channel that the flits are mapped to; sending the flits according to the multiple cycles to the virtual channel; selecting the virtual channel for sending the flits to the router via the physical channel; wherein determining the flit sequence by linked-list management and priority routing.
  2. 2 . The computer-implemented method as claimed in claim 1 , wherein distributing the flits to the plurality of virtual channel First In First Out (FIFOs) based on each virtual channel FIFOs credit indication.
  3. 3 . The computer-implemented method as claimed in claim 1 , wherein the flits from the router to the destination node is transmitted as a request flit or a data flit.
  4. 4 . The computer-implemented method as claimed in claim 1 , wherein the flits from the destination node to the router is transmitted as a response flit or a data flit.
  5. 5 . The computer-implemented method as claimed in claim 1 , wherein selecting the virtual channel by arbitration for sending the flits to the router via the physical channel.
  6. 6 . The computer-implemented method as claimed in claim 1 , wherein the method further comprises generating variables by a linked-list manager to determine destination of the flits before transmitting the flits from the router to the destination node.
  7. 7 . The computer-implemented method as claimed in claim 6 , wherein creating a sequence of the flits forming a linked-list once the variables are generated.
  8. 8 . The computer-implemented method as claimed in claim 1 , wherein the priority routing comprising priority elevation of the flits in a linked-list when a higher priority flit is enqueued into the linked-list.
  9. 9 . An apparatus for data transmission for a Network-on-Chip, comprising: a processor; and a non-transitory computer readable medium comprising computer-executable instructions that, when executed by the processor, cause the apparatus to perform the method as claimed in claim 1 .

Description

TECHNICAL FIELD The present invention relates to data transferring which allows scalable high performance networking on and off chip, more particularly to a data transmission packetization and routing in a network-on-chip (NOC). BACKGROUND ART Network-on-Chip (NoC) is a new paradigm for System-on-Chip (SoC) design. Increasing integration produces a situation where bus structure, which is commonly used in System-on-Chip, becomes blocked and increased capacitance that poses physical problems. Hence, the traditional data transferring method via bus architecture is replaced in Network-on-Chip architecture for improving the system performance, whereby data communications between segments of chip are packetized and transferred through the network. The network consists of wires and routers. Processors, memories and other IP-blocks (Intellectual Property) are connected to routers. A routing algorithm plays a significant role on network's operation. Routers make the routing decisions based on the routing algorithm. Although Network-on-Chip has been widely used to improve the data network performance particularly solving data latency and/or congestion problem, it still suffers from some issues and drawbacks especially blocked traffic due to incapability to prioritize packetized data in router algorithm. This occurrence will then result in a slower data transferring. There have been a number of solutions provided for data transferring for Network-on-Chip in which few of them are discussed below: U.S. Pat. No. 8,711,867B2 disclosed a method which includes receiving flits forwarded from an upstream router into a first input virtual channel (VC) associated with an input port. The flits are associated with packets originated from a first Intellectual Property (IP) core and forwarded to a second IP core. The flits are stored in a VC storage associated with the first input VC. The method further includes performing link width conversion based on a width of the flits being different from a width of an output port. Link width conversion includes accumulation of the flits when the width of the output port is wider and unpacking of the flits when the width of the output port is narrower. Credits are generated based on the flits being forwarded from the first input VC to the output port. The credits are sent to the upstream router to enable receiving more flits from the upstream router. Kavya K. study Network on chip (NoC) linked-list based router for packet classification application where the transactions need to be restored within the time frame (Kavya, K. (2020) “NOC linked-list based router for Packet Classification Application,” International Journal of Engineering Research and, V9(07). Available at: https://doi.org/10.17577/ijertv9is070295). NoC includes virtual channels to improve the performance of the NoC System. When there are multiple transactions, they share the same physical layer and each virtual channel needs a first-in, first-out (FIFO) and every virtual channel is not used every time, so there is no effective utilization. This leads to complexity in software. This study provides a solution to overcome the complexity issue; however the study did not clearly discuss the mechanism of the flit assembler or flit splitter which contributes to the speed of data transmission. Mello, A et. al. study implementation of a mechanism to reduce performance penalization due to packet concurrence for network resources in Networks on chip (NoC). NoC draws on concepts inherited from distributed systems and computer networks subject areas to interconnect IP cores in a structured and scalable way (Mello, A. et al. (2005) “Virtual channels in networks on chip: Implementation and evaluation on hermes NOC,” 2005 18th Symposium on Integrated Circuits and Systems Design [Preprint]. Available at: https://doi.org/10.1109/sbcci.2005.4286853). Congestion in NoC reduces the overall system performance. This effect is particularly strong in networks where a single buffer is associated with each input channel, which simplifies router design, but prevents packets from sharing a physical channel at any given instant of time. The growing number of on-chip cores requires the introduction of an efficient communication structure such as NoC (Gharan, M. O. and Khan, G. N. (2014) “Packet-based adaptive virtual channel configuration for NOC systems,” Procedia Computer Science, 34. Available at: https://doi.org/10.1016/j.procs.2014.07.069). In NoC design, the channel buffer organization facilitates the use of Virtual Channels (VC) for on-chip communication. A VC structure can be categorized as static or dynamic. In a dynamic VC structure, variable numbers of buffer-slots can be employed by each VC according to different traffic conditions in the NoC. Nevertheless, the references described above and other existing techniques still suffer from a number of problems of which the objectives and features of the present invention attempts to address. For exampl