US-12621361-B2 - Systems and methods for controlling high speed video

Abstract

Systems and methods transfer video data to an image processing system from a video source. Pixel data is received in a local buffer of a network interface controller and provided in a video transport packet. The video transport packet includes the pixel data, a media access control header and a video header. The video transport packet is received by another network interface controller that provides the pixel data directly into a video frame buffer of the image processing system.

Inventors

• Dmitrii Loukianov

Assignees

• AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED

Dates

Publication Date

20260505

Application Date

20240429

Claims (20)

1. 1 . A device, comprising: a data buffer configured to receive pixel data from a video interface; a first controller configured to provide packets for a network interface, the packets comprising the pixel data; and a second controller configured to monitor a fullness status of the data buffer and trigger the first controller to build a packet when enough data is available, wherein a portion of the pixel data for the packet is not removed from the data buffer for a time window when the portion can be retransmitted on request, wherein the second controller is configured to receive video streaming control protocol messages from an Ethernet network via the network interface, wherein at least one of the messages is interpreted in hardware and configured to trigger retransmission of the portion if the at least one of the messages arrived within the time window.
2. 2 . The device of claim 1 , wherein the second controller is configured to provide the packet without host processor software recopying or reformatting the pixel data.
3. 3 . The device of claim 1 , wherein the packet is configured for communication on a packet network, the packet network being a high speed Ethernet.
4. 4 . The device of claim 1 , wherein the first controller is coupled to a video streaming controller.
5. 5 . The device of claim 1 , wherein the second controller is a video control protocol controller.
6. 6 . The device of claim 1 , wherein the portion is temporarily stored in a shadow buffer.
7. 7 . The device of claim 1 , further comprising a camera comprising the video interface.
8. 8 . The device of claim 1 , wherein the data buffer is a first in, first out memory.
9. 9 . The device of claim 1 , where the data buffer stores four portions.
10. 10 . A device, comprising: a system memory configured to receive pixel data from a video source; a first controller configured to provide packets for a network interface using packet creation hardware, the packets comprising the pixel data; and a second controller configured to monitor a fullness status of a data buffer and trigger the first controller to build a packet when enough data is available, wherein a portion of the pixel data for the packet is not removed from the data buffer for a time window when the portion can be retransmitted on request, wherein the second controller is configured to receive video streaming control protocol messages from an Ethernet network via the network interface, wherein at least one of the messages is interpreted in hardware and configured to trigger retransmission of the portion if the at least one of the messages arrived within the time window.
11. 11 . The device of claim 10 , wherein the second controller is configured to provide the packet without host processor software recopying or reformatting the pixel data.
12. 12 . The device of claim 10 , wherein the second controller is configured to provide the packet without host processor software recopying or reformatting the pixel data.
13. 13 . The device of claim 10 , wherein the packet is configured for communication on a packet network, the packet network being a high speed Ethernet.
14. 14 . The device of claim 10 , wherein the device is a single chip device or a system on a chip.
15. 15 . The device of claim 10 , wherein the portion is temporarily stored in a shadow buffer in the system memory.
16. 16 . The device of claim 10 , wherein the second controller is a video control protocol controller.
17. 17 . A method of transferring video data to an image processing system from a video source, the method comprising: receiving pixel data from a video interface to a data buffer; providing packets for a network interface, the packets comprising the pixel data; monitor a fullness status of the data buffer and triggering a packet to be built when enough data is available, wherein a portion of the pixel data for the packet is not removed from the data buffer for a time window when the portion can be retransmitted on request, wherein first pixel data of the pixel data is transmitted when at least an entire portion of the pixel data is stored and is sent to a network at a network data rate higher than a data rate of the video interface; and receiving video streaming control protocol messages from an Ethernet network via the network interface, wherein at least one of the messages is interpreted in hardware and configured to trigger retransmission of the portion if the at least one of the messages arrived within the time window.
18. 18 . The method of claim 17 , wherein the packet is provided without host processor software recopying or reformatting the pixel data.
19. 19 . The method of claim 17 , wherein a video control protocol controller receives the video streaming control protocol messages.
20. 20 . The method of claim 17 , further comprising: temporarily storing the portion in a shadow buffer in the data buffer.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is a continuation of U.S. patent application Ser. No. 17/979,381, filed Nov. 2, 2022, which is a continuation of U.S. patent application Ser. No. 17/390,324 (now U.S. Pat. No. 11,522,931), filed Jul. 30, 2021, both of which are incorporated by reference herein their entireties. FIELD OF THE DISCLOSURE This disclosure generally relates to systems for and methods of implementing digital video transport in a packet data network environment, including but not limited to, environments that use high speed video transport in an Ethernet network. Some embodiments in the disclosure relate to a network interface controller configured for efficient video transport between a digital video source and a networked video processor. BACKGROUND OF THE DISCLOSURE Packet networks are used to distribute data packets based on address information contained within each data packet. For example, Ethernet networks transfer digital data using packets, which contain fragmented picture payload data in the form of pixel brightness values and framing and other supplementary information between the picture payload data. Processing a pixel stream received from the Ethernet network through a conventional network interface controller (NIC) into a collection of network packet data buffers in an image processing system can be inefficient due at least in part to the need to copy the fragmented payload from network buffers into the pure video buffers expected by video applications. BRIEF DESCRIPTION OF THE DRAWINGS Various objects, aspects, features, and advantages of the disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which reference characters identify corresponding elements throughout. In the drawings, like reference numbers generally indicate identical, functionally similar, and/or structurally similar elements. FIG. 1 is a general schematic block diagram of a video transport system according to some embodiments; FIG. 2 is a general schematic block diagram of video frame buffer in host system memory in the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 3 is a general schematic block diagram of a set of buffers layout and a buffer descriptor table in host system memory of the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 4 is a general schematic block diagram of a sequence of packets used in the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 5 is a general schematic block diagram of video stream protocol packet structures for the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 6 is a schematic block diagram of picture buffer maps for tracking the progress of reception of the video transport packets illustrated in FIG. 4 for use in the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 7 is a schematic block diagram of a video source host processing system and network interface controller for use in the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 8 is a schematic block diagram of a video source host processing system and network interface controller for use in the video transport system illustrated in FIG. 1 according to some embodiments; FIG. 9 is a schematic block diagram of a video destination host processing system and network interface controller for use in the video transport system illustrated in FIG. 1 according to some embodiments; and FIG. 10 is a schematic block diagram of a network interface controller for use in the video transport system illustrated in FIG. 1 according to some embodiments. The details of various embodiments of the methods and systems are set forth in the accompanying drawings and the description below. DETAILED DESCRIPTION The following IEEE standard(s), including any draft versions of such standard(s), are hereby incorporated herein by reference in their entirety and are made part of the present disclosure for all purposes: IEEE P802.3™ and IEEE Ethernet standard systems including but not limited to LRM, VSR, SR, MR, LR, ZR and KR. Although this disclosure may reference aspects of these standard(s), the disclosure is in no way limited by these standard(s). Some embodiments relate to network interface controller for transferring pixel data from a video source. The network interface controller includes a Master Agent interface configured to be coupled to the video source, and a video transport accelerator configured to receive the pixel data into a local buffer and provide a video transport packet. The video transport packet comprises the pixel data, a media access control header and a video header in some embodiments. Some embodiments relate to a network interface controller that transfers video data to an image processing system. The network interface