US-12621364-B2 - Remote mapping of circuit speed variation due to process, voltage and temperature using a network of digital sensors

US12621364B2US 12621364 B2US12621364 B2US 12621364B2US-12621364-B2

Abstract

A digital sensor network is overlaid on an integrated circuit for identifying and mapping hotspots in the integrated circuit. The digital sensor network may include a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit. Each of the plurality of digital sensors may include a ring oscillator and may be configured to output a counter value of a ring oscillator counted over a designated period. A sensor network control unit may be provided that is communicatively connected to the plurality of digital sensors via a communication circuit. The sensor network control unit may be configured to receive a plurality of counter values including the counter value from each of the plurality of digital sensors and identify a hotspot within the area of the integrated circuit.

Inventors

Bogdan Tutuianu
Osamu Takahashi

Assignees

TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED

Dates

Publication Date: 20260505
Application Date: 20230321

Claims (20)

1 . A digital sensor network, comprising: a plurality of digital sensors distributed within an area of an integrated circuit component of an integrated circuit, the plurality of digital sensors including: a first tile of digital sensors including a first plurality of perimeter digital sensors and a first center digital sensor located within the first plurality of perimeter digital sensors, wherein adjacent perimeter digital sensors of the first plurality of perimeter digital sensors are disposed approximately a first distance apart that is as close as possible to a distance at which an environmental condition measured using the plurality of digital sensors decays by approximately half given layout restrictions by circuits of the integrated circuit component, and a distance between the first center digital sensor and a side of the first tile is one-half the first distance.
2 . The digital sensor network of claim 1 , wherein the plurality of digital sensors further comprises: a second tile of digital sensors including a second plurality of perimeter digital sensors and a second center digital sensor; and the first center digital sensor and the second center digital sensor are disposed approximately the first distance apart.
3 . The digital sensor network of claim 1 , wherein the first plurality of perimeter digital sensors includes a perimeter digital sensor and the plurality of digital sensors further comprises a second tile of digital sensors including a second plurality of perimeter digital sensors including the perimeter digital sensor and a second center digital sensor.
4 . The digital sensor network of claim 1 , wherein the plurality of digital sensors further comprises a second tile of digital sensors including a second plurality of perimeter digital sensors including the first center digital sensor and a second center digital sensor including a perimeter digital sensor of the first plurality of perimeter digital sensors.
5 . The digital sensor network of claim 1 , wherein: the first plurality of perimeter digital sensors and the first center digital sensor are disposed such that a hotspot of the environmental condition within the tile is within a half tile width diameter of the first center digital sensor.
6 . The digital sensor network of claim 1 , wherein the environmental condition is temperature.
7 . The digital sensor network of claim 1 , further comprising: a sensor network control unit communicatively coupled to the plurality of digital sensors, wherein the plurality of digital sensors generate a plurality of sensor output signals and the sensor network control unit is configured to determine a hotspot in the integrated circuit based on the plurality of sensor output signals.
8 . The digital sensor network of claim 7 , wherein the environmental condition includes at least one of process speed, temperature, or voltage in the integrated circuit component, and the plurality of sensor output signals are based on the measured condition.
9 . The digital sensor network of claim 7 , wherein a sensor output signal of the plurality of sensor output signals comprises a measurement value and a sensor identifier identifying a digital sensor of the plurality of digital sensors that generated the sensor output signal.
10 . The digital sensor network of claim 7 , wherein the plurality of digital sensors includes: a ring oscillator configured to generate a ring oscillator signal in response to a trigger signal; a counter configured to generate a counter value signal representing a counter value of the ring oscillator signal; and a counter storage configured to: store the counter value; and generate a sensor output signal of the plurality of sensor output signals representing the stored counter value.
11 . The digital sensor network of claim 10 , wherein the plurality of digital sensors further comprises a storage signal synchronizer configured to generate a clear counter signal in response to the trigger signal and the ring oscillator signal, and the counter storage is further configured to generate the sensor output signal in response to the clear counter signal.
12 . The digital sensor network of claim 7 , wherein the integrated circuit comprises a plurality of integrated circuit components including the integrated circuit component, and the plurality of digital sensors are distributed in the plurality of integrated circuit components.
13 . The digital sensor network of claim 12 , wherein the plurality of integrated circuit components comprises at least one of a processor, a memory, an intellectual property (IP) unit, a networking unit or an input/output (I/O) unit, and the plurality of digital sensors are distributed in a grid-like pattern in the plurality of integrated circuit components.
14 . The digital sensor network of claim 13 , wherein the grid-like pattern comprises a plurality of tiles comprising the first tile, and the sensor network control unit identifies a tile of the plurality of tiles having a center digital sensor closest to the hotspot as a critical tile.
15 . A digital sensor network, comprising: a plurality of digital sensors distributed in a tile pattern within an integrated circuit component of an integrated circuit, wherein the plurality of digital sensors comprises: a first tile including a plurality of first perimeter digital sensors and a first center digital sensor located at a center of the first tile, wherein adjacent perimeter digital sensors of the plurality of first perimeter digital sensors are separated by a first distance and a distance between the first center digital sensor and a side of the first tile is one-half the first distance; and a second tile including a plurality of second perimeter digital sensors and a second center digital sensor located at a center of the second tile, wherein adjacent perimeter digital sensors of the plurality of second perimeter digital sensors are separated by the first distance and a distance between the second center digital sensor and a side of the second tile is one-half the first distance, wherein a side length of the first tile and the second tile is substantially equal to a distance over which a condition to be measured by the plurality of digital sensors decays by half.
16 . The digital sensor network of claim 15 , wherein a digital sensor of the plurality of digital sensors comprises ring oscillator, a high speed counter coupled to the ring oscillator, and counter storage coupled to the high speed counter.
17 . The digital sensor network of claim 15 , wherein the first tile overlaps with the second tile such that: at least one perimeter digital sensor of the first tile comprises a perimeter digital sensor of the second tile; or the first center digital sensor comprises a center digital sensor of the second tile.
18 . A method of forming a digital sensor network, the method comprising: forming a plurality of digital sensors distributed in a tile pattern within an integrated circuit component of an integrated circuit, wherein the forming of the plurality of digital sensors comprises: forming a first tile including a plurality of first perimeter digital sensors and a first center digital sensor located at a center of the first tile, such that adjacent perimeter digital sensors of the plurality of first perimeter digital sensors are separated by a first distance and a distance between the first center digital sensor and a side of the first tile is one-half the first distance; and forming a second tile including a plurality of second perimeter digital sensors and a second center digital sensor located at a center of the second tile, such that adjacent perimeter digital sensors of the plurality of second perimeter digital sensors are separated by the first distance and a distance between the second center digital sensor and a side of the second tile is one-half the first distance, wherein the forming of the plurality of digital sensors is performed such that a side length of the first tile and the second tile is substantially equal to a distance over which a condition to be measured by the plurality of digital sensors decays by half.
19 . The method of claim 18 , wherein a digital sensor of the plurality of digital sensors comprises ring oscillator, a high speed counter coupled to the ring oscillator, and counter storage coupled to the high speed counter.
20 . The method of claim 18 , wherein the first tile overlaps with the second tile such that: at least one perimeter digital sensor of the first tile comprises a perimeter digital sensor of the second tile; or the first center digital sensor comprises a center digital sensor of the second tile.

Description

RELATED APPLICATIONS This application is a continuation U.S. Non-provisional patent application Ser. No. 16/784,482 entitled “Remote Mapping Of Circuit Speed Variation Due To Process, Voltage And Temperature Using A Network Of Digital Sensors” filed Feb. 7, 2020, the entire contents of which are incorporated herein by reference for all purposes. BACKGROUND The electronic circuits operating contemporary electronic devices have become incredibly powerful. The circuits often are capable of performing a large number of calculations per second enabling sophisticated functionality and applications. However, these circuits operate, the circuits demand more voltage and/or current to power their operations. As the current demands increases, the temperature of the circuit (due to the increased current across the resistance) increases. As the temperature of the circuit increases, the overall performance of the circuit may degrade. Therefore, the monitoring of the temperature of a circuit may be useful. When a temperature of a circuit is determined to rise above certain thresholds, steps may be taken to offload certain functions and/or calculations from particular circuits that may be approaching or over threshold temperatures so that the circuit may properly cool off. Traditional process, voltage and temperature on-chip monitoring is done with very accurate analog circuits that are very large, require their own power supply and can be placed sparsely on the chip. Due to the size, power requirements, voltage or temperature sensors are often placed far from the critical circuits and cannot be used to directly measure the speed, voltage or temperature inside the critical areas. BRIEF DESCRIPTION OF THE DRAWINGS The accompanying drawings, which are incorporated herein and constitute part of this specification, illustrate example embodiments of various embodiments, and together with the general description given above and the detailed description given below, serve to explain the features of the claims. Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. FIG. 1 is a component block diagram illustrating an example digital sensor network on an integrated circuit for implementing various embodiments. FIG. 2 is a component block diagram illustrating an example digital sensor suitable for implementing various embodiments. FIG. 3 is a process flow diagram illustrating a method for sensing an environmental condition at a digital sensor according to an embodiment. FIG. 4 is a graph diagram illustrating temperature decay on an integrated circuit. FIG. 5 is a component block diagram illustrating an example digital sensor network on an integrated circuit suitable for implementing various embodiments. FIGS. 6A-6D are a component block diagrams illustrating examples of a critical tile of a digital sensor network on an integrated circuit suitable for implementing various embodiments. FIG. 7 is a process flow diagram illustrating a method for self-calibration of a sensor network control unit according to an embodiment. FIG. 8 is a process flow diagram illustrating a method for identifying and mapping hotspots according to an embodiment. FIG. 9 is a component block and process flow diagram illustrating an example sensor network control unit suitable for implementing various embodiments. DETAILED DESCRIPTION The following disclosure provides many different embodiments, or examples, for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. The various embodiments will be described in detail with reference to the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. References made to particular examples and implementations are for illustrative purposes, and are not intended to limit the scope of the claims. Further, spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly. The terms “processor,” “processor core,” “controller,”