US-12621580-B2 - Image sensor and electronic device including the same

Abstract

An image sensor includes a pixel array including a plurality of pixels arranged in a first direction and in a second direction; and a logic circuit configured to drive the plurality of pixels. The logic circuit is configured to: generate, based on pixel data corresponding to each of the plurality of pixels, first image data having a first resolution, after generating the first image data, to generate second image data having a second resolution based on binning pixel data corresponding to each of a plurality of binning pixels, the plurality of binning pixels binning two or more pixels adjacent to each other, among the plurality of pixels, the second resolution being lower than the first resolution; and output the first image data and the second image data. A first frames per second of the first image data is lower than a second frames per second of the second image data.

Inventors

• Keunjoo Park
• Mooyoung KIM
• Junseok Kim
• Junhyuk Park
• BongKi SON
• Jiwon Im

Assignees

• SAMSUNG ELECTRONICS CO., LTD.

Dates

Publication Date

20260505

Application Date

20240809

Priority Date

20240103

Claims (18)

1. 1 . An image sensor comprising: a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction; and a logic circuit configured to drive the plurality of pixels, wherein the logic circuit is further configured to: generate, based on pixel data corresponding to each of the plurality of pixels, first image data having a first resolution, after generating the first image data, generate second image data having a second resolution based on binning pixel data corresponding to each of a plurality of binning pixels, the plurality of binning pixels binning two or more pixels adjacent to each other, among the plurality of pixels, the second resolution being lower than the first resolution; and output the first image data and the second image data, wherein a first frames per second of the first image data is lower than a second frames per second of the second image data, wherein a first time period at which the first image data is output and a second time period at which the second image data is output are alternately repeated, and wherein the logic circuit is further configured to output one image frame between the first time period and the second time period, alternately repeated, the one image frame having the second resolution.
2. 2 . The image sensor of claim 1 , wherein each of the plurality of binning pixels corresponds to pixels adjacent to each other in an M×M (M being a natural number of 2 or greater) arrangement among the plurality of pixels.
3. 3 . The image sensor of claim 1 , wherein the one image frame is generated at a rate corresponding to the first frames per second.
4. 4 . The image sensor of claim 1 , further comprising: a memory configured to store the binning pixel data corresponding to an intensity of a light incident on each of the plurality of binning pixels and generated at the second frames per second, wherein the logic circuit is further configured to obtain a difference between a pair of the binning pixel data corresponding to each of the plurality of binning pixels in a pair of consecutive frames, to generate the second image data.
5. 5 . The image sensor of claim 4 , wherein the logic circuit is further configured to convert the binning pixel data corresponding to each of the plurality of binning pixels into a log scale value, and obtain a difference of the log scale value corresponding to each of the plurality of binning pixels in the pair of consecutive frames, to generate the second image data.
6. 6 . The image sensor of claim 5 , wherein the logic circuit is further configured to compare the difference of the log scale value with a predetermined threshold value to generate the second image data.
7. 7 . The image sensor of claim 6 , wherein the logic circuit is further configured to, for each of the plurality of binning pixels, set a pixel value as a first logic value based on the difference of the log scale value being greater than the predetermined threshold value, and set the pixel value as a second logic value based on the difference of the log scale value being less than the predetermined threshold value, and wherein the first logic value and the second logic value are complementary to each other.
8. 8 . The image sensor of claim 1 , wherein the logic circuit is further configured to set an exposure time of each of the plurality of pixels to be longer than an exposure time of each of the plurality of binning pixels.
9. 9 . The image sensor of claim 1 , wherein the logic circuit is further configured to, before generating the first image data, generate third image data having the second resolution at the second frames per second, and wherein the logic circuit is further configured to sequentially output the third image data, the first image data, and the second image data.
10. 10 . An image sensor comprising: a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction; and a logic circuit configured to: generate first image data having a first resolution based on the plurality of pixels; generate a plurality of second image data having a second resolution based on a plurality of binning pixels; generate third image data having the first resolution based on the plurality of pixels; output the first image data; output the plurality of second image data after outputting the first image data; and output the third image data after outputting the plurality of second image data, wherein a first frames per second of the first image data is lower than a second frames per second of the plurality of second image data, wherein the second resolution is lower than the first resolution, wherein a first time period at which the first image data is output and a second time period at which the plurality of second image data is output are alternately repeated, and wherein the logic circuit is further configured to output one image frame between the first time period and the second time period, alternately repeated, the one image frame having the second resolution.
11. 11 . The image sensor of claim 10 , wherein each of the plurality of binning pixels corresponds to pixels adjacent to each other in an M×M (M being a natural number of 2 or greater) arrangement among the plurality of pixels.
12. 12 . The image sensor of claim 10 , wherein the first image data is RGB data and the plurality of second image data is black and white image data.
13. 13 . The image sensor of claim 12 , wherein the plurality of second image data comprises more than 10 second image data frames.
14. 14 . The image sensor of claim 12 , wherein each of the plurality of binning pixels corresponds to more than 8 pixels.
15. 15 . The image sensor of claim 12 , wherein the image imager sensor is configured to output the first image data and the plurality of second image data through the same interface.
16. 16 . The image sensor of claim 15 , wherein the same interface is a mobile industry processor interface (MIPI) interface.
17. 17 . The image sensor of claim 12 , wherein the image sensor is configured to output the first image data and the third image data through a first interface, and wherein the image sensor is configured to output the plurality of second image data through a second interface different from the first interface.
18. 18 . An image sensor comprising: a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction; and a logic circuit configured to: generate first image data having a first resolution based on the plurality of pixels; and generate a plurality of second image data having a second resolution based on a plurality of binning pixels; wherein the second resolution is lower than the first resolution, wherein the first image data is RGB data and the plurality of second image data is black and white image data, wherein a first time period at which the first image data is output and a second time period at which the plurality of second image data is output are alternately repeated, and wherein the logic circuit is further configured to output one image frame between the first time period and the second time period, alternately repeated, the one image frame having the second resolution.

Description

CROSS-REFERENCE TO RELATED APPLICATION(S) This application claims benefit of priority to Korean Patent Application No. 10-2024-0000727 filed on Jan. 3, 2024 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. BACKGROUND One or more example embodiments of the disclosure relate to an image sensor and an electronic device including the same. Image sensors may not only image a subject to generate a two-dimensional image but also be applied in a variety of fields to measure a distance to the subject or generate a three-dimensional image. In particular, in recent years, research has been actively conducted to implement a function of capturing an image by imaging a subject and a function of tracking movement of the subject or measuring a distance to the subject with a single image sensor. SUMMARY One or more example embodiments of the disclosure provide an image sensor capable of generating image data of different resolutions and different numbers of frames per second from a single pixel array, thereby outputting a video having a high resolution and a high frames per second, or reducing shaking of a subject, and an electronic device including the same. According to an aspect of an example embodiment of the disclosure, there is provided an image sensor including: a pixel array including a plurality of pixels arranged in a first direction and in a second direction, the second direction intersecting the first direction; and a logic circuit configured to drive the plurality of pixels, wherein the logic circuit is further configured to: generate, based on pixel data corresponding to each of the plurality of pixels, first image data having a first resolution, after generating the first image data, to generate second image data having a second resolution based on binning pixel data corresponding to each of a plurality of binning pixels, the plurality of binning pixels binning two or more pixels adjacent to each other, among the plurality of pixels, the second resolution being lower than the first resolution; and output the first image data and the second image data, and wherein a first frames per second of the first image data is lower than a second frames per second of the second image data. According to an aspect of an example embodiment of the disclosure, there is provided an electronic device including: an image sensor configured to sequentially output first image data having a first resolution and second image data having a second resolution, the second resolution being lower than the first resolution; and a processor configured to output a result image using the first image data and the second image data, wherein the image sensor includes a pixel array, the pixel array including a plurality of pixels having a same structure, and wherein the image sensor is further configured to, based on pixel data obtained from each of the plurality of pixels exposed to a light for a first exposure time, generate the first image data, and based on binning pixel data obtained from each of a plurality of binning pixels binning two or more pixels adjacent to each other, among the plurality of pixels, exposed to a light for a second exposure time, shorter than the first exposure time, to generate the second image data. According to an aspect of an example embodiment of the disclosure, there is provided a processor including: an interface configured to receive image data from an image sensor; and an image signal processor configured to process the image data to generate a result image, wherein the interface is configured to receive first image data having a first resolution and a first frames per second, and second image data having a second resolution and a second frames per second, wherein the first resolution is higher than the second resolution, and the first frames per second is slower than the second frames per second, and wherein the image signal processor is configured to process the first image data using the second image data, to generate the result image. BRIEF DESCRIPTION OF DRAWINGS The above and other aspects, features, and advantages of certain example embodiments of the disclosure will be more clearly understood from the following detailed description, taken in conjunction with the accompanying drawings, in which: FIG. 1 is a block diagram schematically illustrating an electronic device including an image sensor according to one or more example embodiments. FIG. 2 is a view schematically illustrating a portion of a pixel array included in an image sensor according to one or more example embodiments. FIG. 3 is a circuit diagram schematically illustrating a pixel disposed in a pixel array of an image sensor according to one or more example embodiments. FIG. 4 is a view schematically illustrating a portion of a pixel array included in an image sensor according to one or more example embodiments. FIG. 5 is a circuit diagram schematically illustrating a pix