US-12621582-B2 - Solid-state image sensor, imaging apparatus, and control method for solid-state image sensor

US12621582B2US 12621582 B2US12621582 B2US 12621582B2US-12621582-B2

Abstract

Provided is a solid-stage image sensor of the voltage domain type. The image sensor includes a transfer transistor, a reset transistor, a pre-stage amplification transistor, and a vertical scanning circuit. The reset transistor transfers charge from a photoelectric conversion element to a floating diffusion layer. The reset transistor initializes the floating diffusion layer. The pre-stage amplification transistor amplifies and outputs a voltage of the floating diffusion layer. A plurality of capacitive elements hold the outputted voltage. The vertical scanning circuit performs soft reset on the pre-stage amplification transistor when a reset level that is the voltage when the floating diffusion layer is initialized is to be held in any one of the plurality of capacitive elements.

Inventors

Kenichirou Anjyou

Assignees

SONY SEMICONDUCTOR SOLUTIONS CORPORATION

Dates

Publication Date: 20260505
Application Date: 20220916
Priority Date: 20211018

Claims (10)

1 . A solid-state image sensor, comprising: a transfer transistor configured to transfer charge from a photoelectric conversion element to a floating diffusion layer, wherein a transfer signal is input to a gate of the transfer transistor; a reset transistor configured to initialize the floating diffusion layer, wherein a reset signal is input to a gate of the reset transistor, and the transfer signal and the reset signal are controllable to one of a high level, a middle level, and a low level, wherein the middle level is lower than the high level, and the low level is lower than the middle level; a pre-stage amplification transistor configured to: amplify a first voltage of the floating diffusion layer; and output the amplified first voltage of the floating diffusion layer; a plurality of capacitive elements configured to hold the outputted amplified first voltage of the floating diffusion layer; and a vertical scanning circuit configured to: perform soft reset on the pre-stage amplification transistor in a case where a reset level is to be held in one of the plurality of capacitive elements, wherein the reset level is a voltage at which the floating diffusion layer is initialized; in the case where the reset level is to be held, control the transfer signal and the reset signal from the middle level to the low level; and control the transfer signal and the reset signal from the low level to the middle level immediately before the charge is transferred.
2 . The solid-state image sensor according to claim 1 , further comprising: a plurality of selection transistors configured to connect a first end of a first capacitive element of the plurality of capacitive elements to a post-stage node; and a post-stage reset transistor configured to initialize the post-stage node, wherein second ends of second capacitive elements of the plurality of capacitive elements are connected in common to a pre-stage node to which the voltage is inputted, and in the case where the reset level is to be held, the vertical scanning circuit is further configured to: control the post-stage reset transistor to an on state; and perform the soft reset on the pre-stage amplification transistor.
3 . The solid-state image sensor according to claim 2 , wherein the plurality of selection transistors is pMOS (p-channel Metal Oxide Semiconductor) transistors.
4 . The solid-state image sensor according to claim 2 , wherein the post-stage reset transistor is a pMOS transistor.
5 . The solid-state image sensor according to claim 2 , further comprising: a switching transistor configured to open and close between a source of the pre-stage amplification transistor and the pre-stage node; and a precharge transistor configured to open and close a path between the pre-stage node and a current source.
6 . The solid-state image sensor according to claim 1 , further comprising: a first semiconductor chip; and a second semiconductor chip, wherein the transfer transistor, the reset transistor, and the pre-stage amplification transistor are the first semiconductor chip, and the plurality of capacitive elements and the vertical scanning circuit are on the second semiconductor chip.
7 . The solid-state image sensor according to claim 1 , further comprising a conversion efficiency controlling transistor configured to control charge-voltage conversion efficiency of the floating diffusion layer.
8 . The solid-state image sensor according to claim 1 , further comprising a selector configured to supply one of a power supply voltage or a second voltage, different from the power supply voltage, to a drain of the pre-stage amplification transistor.
9 . An imaging apparatus, comprising: a transfer transistor configured to transfer charge from a photoelectric conversion element to a floating diffusion layer, wherein a transfer signal is input to a gate of the transfer transistor; a reset transistor configured to initialize the floating diffusion layer, wherein a reset signal is input to a gate of the reset transistor, and the transfer signal and the reset signal are controllable to one of a high level, a middle level, and a low level, wherein the middle level is lower than the high level, and the low level is lower than the middle level; a pre-stage amplification transistor configured to: amplify a voltage of the floating diffusion layer; and output the voltage of the floating diffusion layer; a plurality of capacitive elements configured to hold the outputted voltage of the floating diffusion layer; a vertical scanning circuit configured to: perform soft reset on the pre-stage amplification transistor in a case where a reset level is to be held in one of the plurality of capacitive elements, wherein the reset level is a voltage at which the floating diffusion layer is initialized; in the case where the reset level is to be held, control the transfer signal and the reset signal from the middle level to the low level; and control the transfer signal and the reset signal from the low level to the middle level immediately before the charge is transferred; and a signal processing section configured to convert the voltage held in the plurality of capacitive elements into a digital signal.
10 . A control method for a solid-state image sensor, comprising: inputting a transfer signal to a gate of a transfer transistor; transferring, by the transfer transistor, charge from a photoelectric conversion element to a floating diffusion layer based on the transfer signal; inputting a reset signal to a gate of a reset transistor, wherein the transfer signal and the reset signal are controllable to one of a high level, a middle level, and a low level, wherein the middle level is lower than the high level, and the low level is lower than the middle level; initializing, by the reset transistor, the floating diffusion layer to which the charge is transferred from the photoelectric conversion element; amplifying, by a pre-stage amplification transistor, a voltage of the floating diffusion layer; outputting, by the pre-stage amplification transistor, the voltage of the floating diffusion layer; holding, by a plurality of capacitive elements, the voltage outputted from the pre-stage amplification transistor; performing soft reset on the pre-stage amplification transistor in a case where a reset level is to be held in one of the plurality of capacitive elements, wherein the reset level is a voltage at which the floating diffusion layer is initialized; in the case where the reset level is to be held, controlling the transfer signal and the reset signal from the middle level to the low level; and controlling the transfer signal and the reset signal from the low level to the middle level immediately before the charge is transferred.

Description

CROSS REFERENCE TO RELATED APPLICATIONS This application is a U.S. National Phase of International Patent Application No. PCT/JP2022/034705 filed on Sep. 16, 2022, which claims priority benefit of Japanese Patent Application No. JP 2021-170376 filed in the Japan Patent Office on Oct. 18, 2021, which claims priority benefit of Japanese Patent Application No. JP 2021-175889 filed in the Japan Patent Office on Oct. 27, 2021. Each of the above-referenced applications is hereby incorporated herein by reference in its entirety. TECHNICAL FIELD The present technology relates to a solid-state image sensor. Particularly, the present technology relates to a solid-state image sensor of the global shutter type, an imaging apparatus, and a control method for the solid-state image sensor. BACKGROUND ART In the past, in the CIS (CMOS Image Sensor), used is a global shutter system in which all pixels are exposed to light at the same time in order to suppress rolling shutter distortion. Although, with a charge domain system in which an analog memory for retaining charge is provided for each pixel, the global shutter method can be implemented, the PLS (Parasitic Light Sensitivity) characteristic and so forth degrade. Hence, there has been proposed a solid-state image sensor which uses a voltage domain system by which a capacitive element is provided for each pixel such that a voltage is sampled and held in the capacitive element (for example, refer to NPL 1). CITATION LIST Non Patent Literature [NPL 1]Geunsook Park, et al., A 2.2 μm stacked back side illuminated voltage domain global shutter CMOS image sensor, IEDM 2019. SUMMARY Technical Problem In the prior art described above, improvement of the PLS characteristic and so forth is achieved by use of the voltage domain system. However, the voltage domain system described above has such a problem that switching noise (in other words, kTC noise) is generated when a voltage is sampled and held in a capacitive element and the picture quality is deteriorated by the noise. The present technology has been made in view of such a situation as described above, and it is an object of the present technology to improve the picture quality in a solid-state image sensor of the voltage domain system. Solution to Problem The present technology has been made in order to solve the problem described above, and the first aspect of the present technology resides in a solid-state image sensor including a transfer transistor that transfers charge from a photoelectric conversion element to a floating diffusion layer, a reset transistor that initializes the floating diffusion layer, a pre-stage amplification transistor that amplifies and outputs a voltage of the floating diffusion layer, a plurality of capacitive elements that hold the outputted voltage, and a vertical scanning circuit that performs soft reset of the pre-stage amplification transistor when a reset level that is the voltage when the floating diffusion layer is initialized is to be held in any one of the plurality of capacitive elements, and a control method for the solid-state image sensor. This brings about an effect that noise is reduced. Further, in the first aspect, a transfer signal may be inputted to a gate of the transfer transistor, a reset signal may be inputted to a gate of the reset transistor, the transfer signal and the reset signal may be controlled to any one of a high level, a middle level lower than the high level, and a low level lower than the middle level, and the vertical scanning circuit may control, when the reset level is to be held, the transfer signal and the reset signal from the middle level to the low level and control the transfer signal and the reset signal from the low level to the middle level immediately before the charge is transferred. This brings about an effect that missing of information concerning the reset level is prevented. Further, in the first aspect, the solid-state image sensor may further include a plurality of selection transistors that connect one end of any one of the plurality of capacitive elements to a post-stage node, and a post-stage reset transistor that initializes the post-stage node, the other ends of the plurality of capacitive elements may be connected in common to a pre-stage node to which the voltage is inputted, and when the reset level is to be held, the vertical scanning circuit may control the post-stage reset transistor to an on state and perform soft reset of the pre-stage amplification transistor. This brings about an effect that a voltage is held in each of the plurality of capacitive elements. Further, in the first aspect, the plurality of selection transistors may be pMOS (p-channel Metal Oxide Semiconductor) transistors. This brings about an effect that missing of charge from the capacitive elements is prevented. Further, in the first aspect, the post-stage reset transistor may be a pMOS transistor. This brings about an effect that missing of charge from the c