US-12621586-B2 - Multi-storage gated imaging system

US12621586B2US 12621586 B2US12621586 B2US 12621586B2US-12621586-B2

Abstract

A gated imaging system includes a pulsed illuminator configured to generate a plurality of light pulses and a pixel circuit. The pixel circuit includes a photodiode configured to collect photogenerated image charge in response to incident light, a floating diffusion coupled to receive the image charge from the photodiode, a sense node amplifier includes a gate terminal coupled to the floating diffusion, and a storage network coupled between the photodiode and the floating diffusion. The storage network includes a plurality of memory nodes coupled between the photodiode and the floating diffusion in parallel. The storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.

Inventors

Tomas Geurts

Assignees

OMNIVISION TECHNOLOGIES, INC.

Dates

Publication Date: 20260505
Application Date: 20230707

Claims (20)

1 . A gated imaging system, comprising: a pulsed illuminator configured to generate a plurality of light pulses; and a pixel circuit, comprising: a photodiode configured to collect photogenerated image charges in response to incident light, a floating diffusion coupled to receive the image charges from the photodiode, a sense node amplifier coupled to the floating diffusion, a storage network coupled between the photodiode and the floating diffusion, the storage network comprising a plurality of memory nodes coupled between the photodiode and the floating diffusion, and a transfer transistor coupling the photodiode to each of the plurality of memory nodes, wherein the storage network is configured to capture a plurality of depth slices between two successive ones of the light pulses.
2 . The gated imaging system of claim 1 , wherein each of the memory nodes is configured to pulse for a corresponding one of the depth slices between the two successive ones of the light pulses.
3 . The gated imaging system of claim 1 , wherein individual ones of the memory nodes comprise a transistor or a diode.
4 . The gated imaging system of claim 1 , wherein the pixel circuit further comprises a photodiode reset transistor coupled between the photodiode and a voltage source, wherein the photodiode reset transistor is configured to reset the photodiode each time the storage network captures one of the depth slices.
5 . The gated imaging system of claim 1 , wherein the pixel circuit further comprises a network reset transistor coupled between the storage network and a voltage source, wherein the network reset transistor is configured to reset the storage network at an end of a readout period.
6 . The gated imaging system of claim 1 , further comprising a readout circuit coupled to the pixel circuits and configured to read out the depth slices after the storage network captures the depth slices between two successive ones of the light pulses.
7 . The gated imaging system of claim 1 , wherein the pixel circuit is one of a plurality of pixel circuits included in a pixel array.
8 . The gated imaging system of claim 1 , wherein the floating diffusion comprises a plurality of floating diffusion portions, wherein each floating diffusion portion is coupled to at least one of the memory nodes.
9 . The gated imaging system of claim 1 , wherein the sense node amplifier comprises a source follower transistor, wherein the floating diffusion is coupled to a gate terminal of the source follower transistor.
10 . The gated imaging system of claim 1 , wherein the transfer transistor couples the photodiode directly to each of the plurality of memory nodes.
11 . The gated imaging system of claim 1 , wherein: the floating diffusion is a first floating diffusion; the pixel circuit further comprises a second floating diffusion different from the first floating diffusion; and the storage network further comprises one or more second memory nodes coupled between the photodiode and the second floating diffusion.
12 . A gated imaging system, comprising: a pulsed illuminator configured to generate a plurality of light pulses; and a pixel circuit, comprising: a photodiode configured to collect photogenerated image charges in response to incident light; and a plurality of depth slice storage circuits coupled to receive the photogenerated image charges from the photodiode, each depth slice storage circuit comprising: an independent floating diffusion coupled to receive the image charges from the photodiode; an independent sense node amplifier coupled to the independent floating diffusion; at least one independent memory node coupled between the photodiode and the independent floating diffusion; and an independent row select transistor coupled to the independent sense node amplifier, wherein the independent row select transistors of the plurality of depth slice storage circuits couple the independent sense node amplifiers to a same bitline, and wherein the depth slice storage circuits are configured to capture a plurality of depth slices between two successive ones of the light pulses.
13 . The gated imaging system of claim 12 , wherein each independent memory node is configured to pulse for a corresponding one of the depth slices between the two successive ones of the light pulses.
14 . The gated imaging system of claim 12 , wherein each depth slice storage circuit further comprises an independent network reset transistor coupled between the independent floating diffusion and a voltage source, wherein the independent network reset transistor is configured to reset the at least one independent memory node at an end of a readout period.
15 . The gated imaging system of claim 12 , wherein the independent sense node amplifier comprises a source follower transistor, wherein the independent floating diffusion is coupled to a gate terminal of the source follower transistor.
16 . A method of operating a pixel circuit, the method comprising: configuring a pulsed illuminator to generate a plurality of light pulses; coupling a floating diffusion between (i) a photodiode configured to collect photogenerated image charge in response to image light and (ii) a sense node amplifier; coupling a storage network between the photodiode and the floating diffusion, the storage network comprising: a plurality of memory nodes coupled between the photodiode and the floating diffusion; and configuring the storage network to capture (i) a first plurality of depth slices between a first two successive ones of the light pulses and (ii) a second two successive ones of the light pulses, wherein the first plurality of depth slices includes a first number of depth slices, and wherein the second plurality of depth slices includes a second number of depth slices different from the first number.
17 . The method of claim 16 , further comprising: configuring one or more of the memory nodes to pulse for a corresponding one of the depth slices between the first two successive ones of the light pulses.
18 . The method of claim 16 , further comprising: configuring each of the memory nodes to pulse for a corresponding one of the depth slices between the first two successive ones of the light pulses.
19 . The method of claim 16 , wherein individual ones of the memory nodes comprise a transistor or a diode.
20 . The method of claim 16 , further comprising: coupling a photodiode reset transistor between the photodiode and a voltage source; and configuring the photodiode reset transistor to reset the photodiode each time the storage network captures one of the depth slices.

Description

TECHNICAL FIELD This disclosure relates generally to image sensors, and in particular but not exclusively, relates to complementary metal oxide semiconductor (CMOS) image sensors. BACKGROUND Image sensors have become ubiquitous and are now widely used in digital cameras, cellular phones, security cameras, as well as in medical, automotive, and other applications. As image sensors are integrated into a broader range of electronic devices, it is desirable to enhance their functionality, performance metrics, and the like in as many ways as possible (e.g., resolution, power consumption, dynamic range) through both device architecture design as well as image acquisition processing. The technology used to manufacture image sensors has continued to advance at a great pace. For example, the demands of higher resolution and lower power consumption have encouraged the further miniaturization and integration of these devices. A typical image sensor operates in response to image light from an external scene being incident upon the image sensor. The image sensor includes an array of pixels having photosensitive elements (e.g., photodiodes) that absorb a portion of the incident image light and generate image charge upon absorption of the image light. The image charge photogenerated by the pixels may be measured as analog output image signals on column bitlines that vary as a function of the incident image light. In other words, the amount of image charge generated is proportional to the intensity of the image light, which is read out as analog image signals from the column bitlines and converted to digital values to produce digital images (e.g., image data) representing the external scene. The analog image signals on the bitlines are coupled to readout circuits, which include input stages having analog-to-digital conversion (ADC) circuits to convert those analog image signals from the pixel array into the digital image signals. BRIEF DESCRIPTION OF THE DRAWINGS Non-limiting and non-exhaustive embodiments of the present disclosure are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified. FIG. 1 illustrates one example of an imaging system in accordance with the teachings of the present disclosure. FIGS. 2A and 2B illustrate schematics of example single-storage pixel circuits in accordance with the teachings of the present disclosure. FIGS. 3A and 3B illustrate schematic of other example multi-storage pixel circuits in accordance with the teachings of the present disclosure. FIG. 4 illustrates a timing diagram of a gated imaging system in accordance with the teachings of the present disclosure. FIG. 5 illustrates a timing diagram of an example single-storage pixel circuit in accordance with the teachings of the present disclosure. FIG. 6 illustrates a timing diagram of an example multi-storage pixel circuit in accordance with the teachings of the present disclosure. Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been drawn to scale. For example, the dimensions of some of the elements in the figures may be exaggerated relative to other elements to help to improve understanding of various embodiments of the present disclosure. In addition, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of the present disclosure. DETAILED DESCRIPTION Examples directed to a gated imaging system with pixel circuits providing improved gated integration are disclosed. In the following description, numerous specific details are set forth to provide a thorough understanding of the examples. One skilled in the relevant art will recognize, however, that the techniques described herein can be practiced without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail in order to avoid obscuring certain aspects. Reference throughout this specification to “one example” or “one embodiment” means that a particular feature, structure, or characteristic described in connection with the example is included in at least one example of the present disclosure. Thus, the appearances of the phrases “in one example” or “in one embodiment” in various places throughout this specification are not necessarily all referring to the same example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more examples. Spatially relative terms, such as “beneath,” “below,” “over,” “under,” “above,” “upper,” “top,” “bottom,” “left,” “