US-12621590-B1 - Push telemetry from external interface

Abstract

An apparatus for transmitting telemetry through an external interface is disclosed. An integrated circuit includes at least one interface circuit configured to communicate on an external interface of the integrated circuit with a plurality of other integrated circuits. The integrated circuit further includes a first control circuit coupled to the at least one interface circuit, a first table circuit. The first control circuit is configured to store telemetry data transmitted by the plurality of other integrated circuits over the external interface in respective table entries of the first table circuit, based on which of the plurality of other integrated circuits transmitted the telemetry data.

Inventors

• Achmed R. Zahir
• Inder M. Sodhi
• TAL KUZI
• Helena D. O'Shea
• Kunal K. Dave
• Doron Rajwan
• Lior Zimet

Assignees

• APPLE INC.

Dates

Publication Date

20260505

Application Date

20230630

Claims (19)

1. 1 . An apparatus, comprising: a particular integrated circuit including: at least one interface circuit configured to communicate on an external interface with a plurality of other integrated circuits; a first table circuit; a first control circuit coupled to the at least one interface circuit and configured to: receive telemetry data pushed to the at least one interface circuit by ones of the plurality of other integrated circuits, wherein the telemetry data includes information indicative of current functional conditions of the ones of the plurality of other integrated circuits; and store the telemetry data pushed by the ones of the plurality of other integrated circuits over the external interface in respective table entries of the first table circuit, based on which of the ones of the plurality of other integrated circuits transmitted the telemetry data; and at least one processor configured to, for a first read transaction, read data from the first table circuit using a read portion of an address space mapped to the first table circuit, wherein a given entry in the first table circuit includes a status field, wherein the first control circuit is further configured to modify a status in the status field based on the first read transaction using the read portion of the address space that addresses the given entry, and wherein the first control circuit is configured to inhibit modification of the status in the status field based on a second read transaction to the given entry using a peek portion of the address space.
2. 2 . The apparatus of in claim 1 , wherein the particular integrated circuit further includes: a plurality of component circuits; and a second control circuit comprising a second table circuit, wherein the second control circuit is configured to store, in the second table circuit, second telemetry data transmitted from ones of the plurality of component circuits.
3. 3 . The apparatus of in claim 2 , wherein the ones of the plurality of component circuits and the second control circuit are included in one or more power domains of the particular integrated circuit that are selectively powered on and off during a time that the particular integrated circuit receives power.
4. 4 . The apparatus of claim 2 , and wherein the first control circuit and the at least one interface circuit are included in a second power domain that operates at any time that the particular integrated circuit receives power.
5. 5 . The apparatus of claim 1 wherein the at least one interface circuit comprises an address remap circuit configured to generate an address to an entry in the first table circuit based on an identifier of a given one of the plurality of other integrated circuits that transmitted a transaction for the first table circuit, the transaction including a second address.
6. 6 . The apparatus of in claim 5 wherein, in response to the transaction being a write transaction, the address remap circuit is configured to map the address to the entry in an update portion of the address space mapped to the first table circuit, wherein the entry is updated in response to the address to the entry being mapped to the update portion.
7. 7 . The apparatus of in claim 6 wherein, in response to the transaction being a read transaction, the address remap circuit is configured to map the address to the entry in the peek portion of the address space mapped to the first table circuit, wherein the entry, when in the peek portion, is readable without causing an update to a first status field of the entry.
8. 8 . The apparatus of in claim 1 wherein the status field includes a new bit, and wherein the first control circuit is further configured to: set the new bit when the given entry is updated; and clear the new bit when the given entry is read.
9. 9 . A method comprising: collecting, by a plurality of integrated circuits, telemetry data that includes information indicative of current functional conditions of the plurality of integrated circuits; transmitting, by a subset of the plurality of integrated circuits to a first integrated circuit of the plurality of integrated circuits, respective portions of the telemetry data, wherein the first integrated circuit is configured to receive the telemetry data via an external interface; and storing the telemetry data, by a first control circuit of the first integrated circuit, in a first table circuit, wherein the storing comprises the first control circuit storing the telemetry data in respective table entries of the first table circuit, based on which of the subset of the plurality of integrated circuits transmitted the telemetry data; reading, for a first read transaction, read data from a given entry in the first table circuit using a read portion of an address space mapped to the first table circuit; modifying a status in a status field of the given entry based on the first read transaction using the read portion of the address space that addresses the given entry; and inhibiting the modification of the status in the status field of the given entry based on a second read transaction to the given entry using a peek portion of the address space.
10. 10 . The method of claim 9 , wherein the first integrated circuit includes a plurality of component circuits, and wherein the method further comprises: transmitting first telemetry data from ones of the plurality of component circuits to a second control circuit of the first integrated circuit, the second control circuit having a second table circuit; and storing the first telemetry data transmitted from the ones of the plurality of component circuits in the second table circuit.
11. 11 . The method of claim 10 , further comprising: operating the first control circuit any time the first integrated circuit is receiving power; and selectively powering the second control circuit on and off during a time the first integrated circuit is receiving power.
12. 12 . The method of claim 9 , further comprising generating, using an address remap circuit, an address to an entry in the first table circuit based on an identifier of a given one of the subset of the plurality of integrated circuits that transmitted a transaction for the first table circuit, the transaction including a second address.
13. 13 . The method of claim 12 further comprising, in response to the transaction being a write transaction: mapping the address to the entry, using the address remap circuit, in an update portion of the address space mapped to the first table circuit; and updating the entry in response to the address being mapped to the update portion.
14. 14 . The method of claim 12 further comprising, in response to the transaction being a read transaction: mapping the address, using the address remap circuit, in the peek portion of the address space mapped to the first table circuit, wherein the entry, when in the peek portion, is readable without causing an update to a first status field of the entry.
15. 15 . The method of claim 9 , further comprising: wherein the status field includes a new bit, and wherein the first control circuit is further configured to: setting the new bit included in the given entry based on an update to the given entry; and clearing the new bit based on the given entry is read.
16. 16 . A system comprising: a plurality of integrated circuits configured to: collect first telemetry data that includes information indicative of current functional conditions of ones of the plurality of integrated circuits; and push the first telemetry data to an external interface; and a system-on-a-chip (SoC) that includes: a plurality of component circuits configured to collect second telemetry data that includes information indicative of current functional conditions of the SOC; an interface circuit configured to communicate with the plurality of integrated circuits through the external interface; a first control circuit coupled to the interface circuit, the first control circuit having a first table circuit, wherein the first table circuit is configured to store, in respective entries of the first table circuit, the first telemetry data transmitted by the ones of the plurality of integrated circuits based on which of the ones of the plurality of integrated circuits transmitted the first telemetry data; and at least one processor configured to, for a first read transaction, read data from the first table circuit using a read portion of an address space mapped to the first table circuit, wherein a given entry in the first table circuit includes a status field; and wherein the first control circuit is configured to: modify a status in the status field based on the first read transaction using the read portion of the address space that addresses the given entry; and inhibit the modification of the status in the status field based on a second read transaction to the given entry using a peek portion of the address space.
17. 17 . The system of claim 16 , wherein the SoC further includes: a second control circuit having a second table circuit, wherein the second control circuit is configured to store, in the second table circuit, the second telemetry data.
18. 18 . The system of claim 17 , wherein the first control circuit is implemented in a first power domain and is configured to operate whenever the SoC is receiving power, and wherein the second control circuit is implemented in a second power domain and is configured to be selectively powered on and off when the SoC is receiving power.
19. 19 . The system of claim 16 , wherein the interface circuit includes an address remap circuit configured to generate an address to an entry in the first table circuit based on an identifier of a given one of the ones of the plurality of integrated circuits that transmitted a transaction for the first table circuit, the transaction including a second address.

Description

PRIORITY The present application claims priority to U.S. Provisional App. No. 63/376,922, entitled “Push Telemetry from External Interface”, filed on Sep. 23, 2022, the disclosure of which is incorporated by reference herein in its entirety. BACKGROUND Technical Field The present disclosure is directed to electronic systems and, more particularly, to recording telemetry data in an electronic system. Description of the Related Art Telemetry data from various components in a digital system can be used by various control loops to determine states at which various components should operate (e.g., on, off, or various performance states), whether the system as a whole should sleep to conserve power, and so on. Telemetry data can include data such as temperature values, voltage readings (e.g., a level of a supply voltage at which a circuit is operating), performance related metrics (e.g., a processing workload), and other information. Using the telemetry information, operation of the digital system may be optimized. Optimizing the operation of the digital system may include conserving power to remain within a given power budget, maintaining temperature to remain within thermal limits, and increasing the performance (in terms of instructions executed) per watt of power expended, among other possibilities. SUMMARY An apparatus for transmitting telemetry through an external interface is disclosed. In one embodiment, an integrated circuit includes at least one interface circuit configured to communicate on an external interface of the integrated circuit with a plurality of other integrated circuits. The integrated circuit further includes a first control circuit coupled to the at least one interface circuit, a first table circuit. The first control circuit is configured to store telemetry data transmitted by the plurality of other integrated circuits over the external interface in respective table entries of the first table circuit, based on which of the plurality of other integrated circuits transmitted the telemetry data. In various embodiments, the integrated circuit further includes a plurality of component circuits and a second control circuit comprising a second table circuit. The second control circuit is configured to store, in the second table circuit, telemetry data transmitted from ones of the plurality of component circuits. Ones of the plurality of component circuits and the second control circuit are included in one or more power domains of the integrated circuit that are selectively powered on and off during a time that the integrated circuit receives power. The first control circuit and the interface circuit are included in a second power domain that operates at any time that the integrated circuit receives power. BRIEF DESCRIPTION OF THE DRAWINGS The following detailed description makes reference to the accompanying drawings, which are now briefly described. FIG. 1 is a block diagram of one embodiment of a system including an integrated circuit (IC) coupled to a plurality of external ICs. FIG. 2 is a block diagram of one embodiment of a system-on-a-chip (SoC). FIG. 3 is a block diagram of one embodiment of an interface circuit. FIG. 4 is a block diagram illustrating a dashboard entry for one embodiment of a dashboard circuit. FIG. 5 is a block diagram of one embodiment of an address space associated with the dashboard. FIG. 6 is a block diagram of one embodiment of an address remap circuit shown during write operations FIG. 7 is a block diagram of one embodiment of an address remap circuit shown during read operations. FIG. 8 is a flow diagram of one embodiment of a method for operating a system in which telemetry data is pushed from a number of ICs to a central location. FIG. 9 is a block diagram of one embodiment of a system including a forwarding circuit for conveying telemetry data to a receiving circuit. FIG. 10 is a block diagram of one embodiment of a system on a chip (SoC) with forwarding circuits from the dashboards. FIG. 11 is a block diagram of an embodiment of a system having multiple ICs with forwarding circuits. FIG. 12 is a flow diagram of one embodiment of a method for operating a system in which at least one IC includes a forwarding circuit. FIG. 13 is a block diagram of one embodiment of an example system. FIG. 14 is a block diagram of one embodiment of a computer accessible storage medium. DETAILED DESCRIPTION OF EMBODIMENTS Various electronic systems include multiple component circuits, which may in some cases be implemented on integrated circuits. These component circuits may accumulate telemetry data that can be used by a power manager in control loops. The power manager may be implemented on a particular one of the integrated circuits, which may obtain the telemetry data from other ones of the component circuits or other integrated circuits. However, there can be significant latency in obtaining the telemetry data by the power manager in which the control loops are managed. This