US-12621927-B2 - Circuit board, semiconductor device, and method for manufacturing semiconductor device

Abstract

A circuit board is a wiring board frame in which a plurality of wiring boards in each of which a pair of lands electrically connected to a capacitor are formed on a first surface are arranged side by side. In the wiring board frame, an inspection path is formed. The inspection path passes between the pair of lands provided on each of the plurality of wiring boards. The inspection path includes a first wiring including one end between the pair of lands, and a second wiring including one end between the pair of lands, and the one end of the first wiring and the one end of the second wiring are formed to be separated from each other.

Inventors

• Takashi Yamamoto
• Soichiro Ibaraki

Assignees

• KIOXIA CORPORATION

Dates

Publication Date

20260505

Application Date

20230307

Priority Date

20220914

Claims (5)

1. 1 . A semiconductor device comprising: a wiring board including a first surface and a second surface that is on an opposite side to the first surface; a semiconductor chip provided on the first surface of the wiring board; an electronic component connected to a pair of electrodes provided on the first surface of the wiring board; sealing resin covering the first surface of the wiring board and surfaces of the semiconductor chip and the electronic component; an external equipment connecting terminal provided on the second surface of the wiring board; and a plurality of wirings, each of the plurality of wirings including a first end, a second end, and a side surface orthogonal to the first surface and the second surface of the wiring board, the first end being on the side surface, and the second end being located between the pair of electrodes, wherein: the plurality of wirings include a first wiring and a second wiring, and between the pair of electrodes, the second end of the first wiring and the second end of the second wiring are formed to be separated from each other.
2. 2 . The semiconductor device according to claim 1 , wherein: the wiring board includes a plurality of wiring layers formed by being stacked between the first surface and the second surface, the plurality of wiring layers include an uppermost layer, the uppermost layer is formed to be exposed from the first surface, and each of the plurality of wirings includes at least a part formed between the pair of electrodes, the part being formed on the uppermost layer.
3. 3 . The semiconductor device according to claim 2 , wherein the electronic component is physically connected to the first wiring and the second wiring by an adhesive member having conductivity.
4. 4 . The semiconductor device according to claim 3 , wherein: a conductor is formed on a surface facing the wiring board, of the electronic component, and the conductor is electrically connected to the first wiring and the second wiring via the adhesive member.
5. 5 . The semiconductor device according to claim 4 , wherein the electronic component is a capacitor.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2022-146022 filed on Sep. 14, 2022; the entire contents of which are incorporated herein by reference. FIELD Embodiments described herein relate generally to a circuit board, a semiconductor device, and a method for manufacturing the semiconductor device. BACKGROUND As a countermeasure for noise during high-speed operation, a semiconductor device has been proposed in which a capacitor as well as a semiconductor chip is provided on a wiring board. However, occurrence of physical poor connections (tombstones, detachments, and the like) between the capacitors and the wiring boards has become a problem. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross-sectional view schematically showing an example of a semiconductor device of an embodiment; FIG. 2A is a schematic view explaining an example of an arrangement of semiconductor chips and capacitors that are mounted on a wiring board of the embodiment, which is a top view of the wiring board on which the semiconductor chips and the capacitors are arranged seen from above a first surface; FIG. 2B is a schematic view explaining the example of the arrangement of the semiconductor chips and the capacitors that are mounted on the wiring board of the embodiment, which is a side view of the wiring board on which the semiconductor chips and the capacitors are arranged seen from a front side in an X direction; FIG. 3 is a plan view explaining an example of an arrangement of an inspection path in the wiring board of the embodiment; FIG. 4 is an enlarged plan view of a rectangular region B surrounded by a dotted line in FIG. 3; FIG. 5 is a plan view explaining an example of a layout of the inspection path in a wiring board frame of the embodiment; FIG. 6 is a cross-sectional view along line C-C of the wiring board frame shown in FIG. 5; FIG. 7 is a view explaining an example of a configuration of the capacitor that is mounted on the semiconductor device of the embodiment; FIG. 8A is a view explaining a manufacturing process of the capacitor in FIG. 7; FIG. 8B is a view explaining the manufacturing process of the capacitor in FIG. 7; FIG. 8C is a view explaining the manufacturing process of the capacitor in FIG. 7; FIG. 9 is a plan view for explaining a positional relationship of the capacitor and the wiring board of the embodiment; FIG. 10 is a cross-sectional view for explaining a configuration of a junction portion of the capacitor and the wiring board of the embodiment; FIG. 11A is a flowchart explaining an example of a manufacturing process of the semiconductor device of the embodiment; FIG. 11B is a flowchart explaining an example of a process of inspecting a physical connection state of capacitors mounted on the wiring board frame of the embodiment; FIG. 12 is a cross-sectional view explaining another arrangement of the inspection path in the wiring board frame of the embodiment; FIG. 13 is a cross-sectional view explaining another arrangement of the inspection path and inspection terminals in the wiring board frame of the embodiment; FIG. 14A is a schematic view explaining another example of the arrangement of semiconductor chips and the capacitors that are mounted on the wiring board of the embodiment, which is a top view of the wiring board on which the semiconductor chips and the capacitors are arranged seen from above the first surface; FIG. 14B is a schematic view explaining the other example of the arrangement of the semiconductor chips and the capacitors that are mounted on the wiring board of the embodiment, which is a side view of the wiring board on which the semiconductor chips and the capacitors are arranged seen from a front side in the X direction; FIG. 15 is a plan view explaining another example of the arrangement of the inspection path in the wiring board of the embodiment; FIG. 16 is a plan view explaining another example of the arrangement of the inspection path in the wiring board frame of the embodiment; FIG. 17 is a cross-sectional view for explaining another configuration of the junction portion of the capacitor and the wiring board of the embodiment; and FIG. 18 is a cross-sectional view for explaining still another configuration of the junction portion of the capacitor and the wiring board of the embodiment. DETAILED DESCRIPTION A circuit board of a present embodiment is a circuit board including a plurality of wiring boards each including a first surface and a second surface that is on an opposite side to the first surface. The plurality of wiring boards are arranged with the first surface of each of the plurality of wiring boards aligned in a same direction. Each of the plurality of wiring boards includes a pair of electrodes electrically connected to an electronic component, on the first surface. In the circuit board, an inspection path is formed. The inspection path includes a first wiri