US-12621933-B2 - Capacitive element, circuit carrier having the same and fabrication method thereof

Abstract

A circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively.

Inventors

• Chun Hung Kuo
• Kuo-Ching Chen
• Yu-Cheng Huang
• Yu-Hua Chen

Assignees

• UNIMICRON TECHNOLOGY CORP.

Dates

Publication Date

20260505

Application Date

20230821

Priority Date

20230726

Claims (17)

1. 1 . A circuit carrier, including: at least one wiring layer; and a capacitive element disposed in at least one dielectric layer of the at least one wiring layer; wherein the capacitive element comprises a lower electrode, an inter-electrode and an upper electrode, the inter-electrode is located between the lower electrode and the upper electrode, the inter-electrode comprises a plate, at least one first finger and at least one second finger, and the at least one first finger and the at least one second finger extend from opposite sides of the plate, respectively; wherein the capacitive element further comprises a first interlayer dielectric and a second interlayer dielectric, the first interlayer dielectric is located between the lower electrode and the inter-electrode, the second interlayer dielectric is located between the inter-electrode and the upper electrode.
2. 2 . The circuit carrier according to claim 1 , wherein the lower electrode comprises a plate and at least one finger, the at least one finger of the lower electrode extends from the plate of the lower electrode toward the plate of the inter-electrode, and the at least one finger of the lower electrode is parallel with the at least one first finger of the inter-electrode.
3. 3 . The circuit carrier according to claim 2 , wherein the at least one finger of the lower electrode overlaps the at least one first finger of the inter-electrode in a length direction of the circuit carrier.
4. 4 . The circuit carrier according to claim 1 , wherein the upper electrode comprises a plate and at least one finger, the at least one finger of the upper electrode extends from the plate of the upper electrode toward the plate of the inter-electrode, and the at least one finger of the upper electrode is parallel with the at least one second finger of the inter-electrode.
5. 5 . The circuit carrier according to claim 4 , wherein the at least one finger of the upper electrode overlaps the at least one second finger of the inter-electrode in a length direction of the circuit carrier.
6. 6 . The circuit carrier according to claim 1 , wherein the at least one first finger and the at least one second finger of the inter-electrode are disposed symmetrically with respect to the plate of the inter-electrode.
7. 7 . The circuit carrier according to claim 1 , wherein the at least one first finger of the inter-electrode completely overlaps the at least one second finger thereof in a thickness direction of the circuit carrier.
8. 8 . The circuit carrier according to claim 1 , wherein the first interlayer dielectric and the second interlayer dielectric are made of different material from the at least one dielectric layer.
9. 9 . The circuit carrier according to claim 1 , wherein each of the lower electrode, the inter-electrode and the upper electrode is a comb electrode.
10. 10 . A capacitive element for circuit carrier, comprising: a lower electrode, an inter-electrode and an upper electrode, wherein the inter-electrode is located between the lower electrode and the upper electrode, the inter-electrode comprises a plate, at least one first finger and at least one second finger, and the at least one first finger and the at least one second finger extend from opposite sides of the plate, respectively; wherein the at least one first finger and the at least one second finger are disposed symmetrically with respect to the plate of the inter-electrode; and wherein the capacitive element further comprises a first interlayer dielectric and a second interlayer dielectric, the first interlayer dielectric is located between the lower electrode and the inter-electrode, the second interlayer dielectric is located between the inter-electrode and the upper electrode.
11. 11 . A fabrication method of a capacitive element for a circuit carrier, comprising: forming a lower electrode and a first interlayer dielectric on a core, wherein the lower electrode is located below the first interlayer dielectric; forming a first dielectric layer on the core, wherein the first dielectric layer exposes the first interlayer dielectric; forming an inter-electrode on the first interlayer dielectric, wherein the inter-electrode comprises a plate, at least one first finger and at least one second finger, the at least one first finger and the at least one second finger extend from opposite sides of the plate, respectively; forming a second interlayer dielectric on the inter-electrode; forming a second dielectric layer on the first dielectric layer, wherein the second dielectric layer exposes the second interlayer dielectric; and forming an upper electrode on the second interlayer dielectric.
12. 12 . The fabrication method according to claim 11 , wherein the forming the lower electrode and the first interlayer dielectric on the core comprises: forming a metal layer on the core; forming the first interlayer dielectric on the metal layer; and removing part of the metal layer to form the lower electrode.
13. 13 . The fabrication method according to claim 12 , wherein the forming the metal layer on the core comprises processing the metal layer by lithography and plating.
14. 14 . The fabrication method according to claim 12 , wherein the metal layer is formed on a wiring area and a capacitor area of the circuit carrier, and the forming the first interlayer dielectric on the metal layer comprises: forming a dielectric material layer on the metal layer, wherein the dielectric material layer is spread over the wiring area and the capacitor area; completely removing the dielectric material layer in the wiring area; and patterning the dielectric material layer in the capacitor area to form the first interlayer dielectric.
15. 15 . The fabrication method according to claim 11 , wherein the forming the inter-electrode on the first interlayer dielectric comprises: forming a metal layer on the first interlayer dielectric; reducing a thickness of the metal layer so as to form the plate and the at least one first finger of the inter-electrode; and forming the at least one second finger of the inter-electrode on the plate.
16. 16 . The fabrication method according to claim 11 , wherein the circuit carrier has a wiring area and a capacitor area, and the forming the second interlayer dielectric on the inter-electrode comprises: forming a dielectric material layer on the first dielectric layer to cover the inter-electrode, wherein the dielectric material layer is spread over the wiring area and the capacitor area; completely removing the dielectric material layer in the wiring area; and patterning the dielectric material layer in the capacitor area to form the second interlayer dielectric.
17. 17 . The fabrication method according to claim 11 , wherein the forming the upper electrode on the second interlayer dielectric comprises: forming a metal layer on the second interlayer dielectric; and reducing a thickness of the metal layer so as to form the upper electrode.

Description

This application claims priority under 35 U.S.C. § 119 (a) on Patent Application No(s). 112127897 filed in Taiwan, R.O.C. on Jul. 26, 2023, the entire contents of which are hereby incorporated by reference. BACKGROUND 1. Technical Field The present disclosure relates to circuit carrier, more particularly to a circuit carrier including capacitive element. 2. Related Art As the demand of electronic products are trending towards multi-functionality, high signal transmission speed and high component density, the functionality of an integrated circuit chip is enhancing, and the number of passive components for a consumer electronic product is also increasing dramatically. A buried capacitive element is one of the essential components in circuit board design. With the development of high-density circuit board, the lack of a buried capacitive element with high capacitance in a limited space is a problem to be solved in this technical field. SUMMARY According to one embodiment of the present disclosure, a circuit carrier includes at least one wiring layer and a capacitive element. The capacitive element is disposed in at least one dielectric layer of the wiring layer. The capacitive element includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least one second finger. The first finger and the second finger extend from opposite sides of the plate, respectively. According to one embodiment of the present disclosure, the lower electrode includes a plate and at least one finger. The finger of the lower electrode extends from the plate of the lower electrode toward the plate of the inter-electrode. The finger of the lower electrode is parallel with the first finger of the inter-electrode. According to one embodiment of the present disclosure, the finger of the lower electrode overlaps the first finger of the inter-electrode in a length direction of the circuit carrier. According to one embodiment of the present disclosure, the upper electrode includes a plate and at least one finger. The finger of the upper electrode extends from the plate of the upper electrode toward the plate of the inter-electrode. The finger of the upper electrode is parallel with the second finger of the inter-electrode. According to one embodiment of the present disclosure, the finger of the upper electrode overlaps the second finger of the inter-electrode in a length direction of the circuit carrier. According to one embodiment of the present disclosure, the first finger and the second finger of the inter-electrode are disposed symmetrically with respect to the plate of the inter-electrode. According to one embodiment of the present disclosure, the first finger of the inter-electrode completely overlaps the second finger of the inter-electrode in a thickness direction of the circuit carrier. According to one embodiment of the present disclosure, the capacitive element further includes a first interlayer dielectric and a second interlayer dielectric. The first interlayer dielectric is located between the lower electrode and the inter-electrode. The second interlayer dielectric is located between the inter-electrode and the upper electrode. The first interlayer dielectric and the second interlayer dielectric are made of different material from the dielectric layer. According to one embodiment of the present disclosure, each of the lower electrode, the inter-electrode and the upper electrode is a comb electrode. According to one embodiment of the present disclosure, a capacitive element for circuit carrier includes a lower electrode, an inter-electrode and an upper electrode. The inter-electrode is located between the lower electrode and the upper electrode. The inter-electrode includes a plate, at least one first finger and at least second finger. The first finger and the second finger extend from opposite sides of the plate, respectively. The first finger and the second finger are disposed symmetrically with respect to the plate of the inter-electrode. According to one embodiment of the present disclosure, a fabrication method of a capacitive element for a circuit carrier includes the following steps: forming a lower electrode and a first interlayer dielectric on a core, wherein the lower electrode is located below the first interlayer dielectric; forming a first dielectric layer on the core, wherein the first dielectric layer exposes the first interlayer dielectric; forming an inter-electrode on the first interlayer dielectric, wherein the inter-electrode comprises a plate, at least one first finger and at least one second finger, the at least one first finger and the at least one second finger extend from opposite sides of the plate, respectively; forming a second interlayer dielectric on the inter-electrode; forming a second dielectric layer on the first dielectric layer, wh